参数资料
型号: MSC7112VM800
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 数字信号处理
英文描述: 32-BIT, 200 MHz, OTHER DSP, PBGA400
封装: 17 X 17 MM, LEAD FREE, BGA-400
文件页数: 15/56页
文件大小: 1489K
代理商: MSC7112VM800
M
SC7
1
2
Low-Cos
t1
6
-bit
DSP
with
DDR
Control
le
rDa
ta
She
e
t,
Re
v
.1
1
Sp
ecifi
cati
ons
Fre
es
c
a
le
Sem
ico
nd
uct
or
22
2.5.2.
5
Core
C
lock
Fre
quency
R
ange
Wh
en
Using
DDR
Mem
ory
Th
ecor
eclock
c
an
als
o
be
limited
by
th
efr
equen
cy
ran
g
eo
fthe
D
R
dev
ices
in
the
s
y
st
em
.
Ta
u
mma
ri
zes
t
h
is
re
st
ri
ct
ion.
2.
5.
3
R
ese
tT
imi
n
g
Th
eMSC
7
1
2
d
ev
ice
h
as
se
v
er
al
in
p
u
ts
to
th
er
eset
lo
g
ic.
All
MS
C7
1
2
r
es
et
so
u
rces
ar
ef
ed
in
to
th
er
eset
co
n
tr
o
ller
,wh
ich
takes
dif
fer
ent
actions
dep
endin
g
on
t
h
es
o
urce
o
fthe
r
es
et.
Th
eres
et
s
tatus
regis
ter
ind
icates
the
mo
st
recen
ts
o
urces
to
ca
us
e
ar
es
et.
Ta
d
esc
rib
es
th
ere
se
tso
u
rc
es
.
Ta
u
mm
arizes
th
eres
et
actions
that
o
ccur
as
a
res
u
lt
of
th
edif
feren
tres
et
s
o
urces
.
T
a
b
le
13.
Resu
lt
in
g
Ra
n
g
es
P
e
rm
it
te
d
fo
rt
h
e
Co
re
Clo
c
k
CLKCTRL[CKSEL
]
C
LKCTRL
[RN
G
]
R
esu
lting
Divis
ion
F
acto
r
Allow
e
d
Rang
e
of
Co
re
Cloc
k
Com
m
e
n
ts
11
1
Reser
v
ed
Reser
v
ed
11
0
2
150
Core_C
lk
200
MH
z
L
imit
ed
by
range
of
PL
L
01
1
2
150
Core_C
lk
200
MH
z
L
imit
ed
by
range
of
PL
L
01
0
4
75
C
ore_Clk
150
M
H
z
L
imit
ed
by
range
of
PL
L
No
te
:
T
h
is
t
able
result
s
f
rom
the
al
lowed
range
f
o
r
F
OU
T ,wh
ic
h
depends
on
clock
s
el
ec
ted
via
CLKCT
R
L[
CKS
E
L]
.
T
a
b
le
14.
Co
re
Clo
ck
Ran
g
es
Wh
en
U
s
in
g
DDR
D
DR
T
y
pe
Allow
e
d
Freq
uenc
y
Ra
nge
for
DDR
CK
Corresp
ondi
ng
Ra
nge
fo
r
the
Co
re
Cloc
k
Com
m
e
n
ts
D
DR
200
(P
C-1600)
83–100
M
H
z
166
core
cl
ock
200
MH
z
C
ore
li
m
ited
t
o
2
×
m
a
ximum
DDR
f
requency
D
DR
266
(P
C-2100)
83–133
M
H
z
166
core
cl
ock
266
MH
z
C
ore
li
m
ited
t
o
2
×
m
a
ximum
DDR
f
requency
D
DR
333
(P
C-2600)
83–150
M
H
z
166
core
cl
ock
300
MH
z
C
ore
li
m
ited
t
o
2
×
m
a
ximum
DDR
f
requency
T
a
b
le
1
5.
Re
set
S
o
u
rce
s
N
a
m
e
D
ir
e
ctio
n
D
es
cr
ipti
on
P
o
wer-o
n
res
e
t
(PO
R
ES
ET
)
Input
In
it
iat
e
s
t
he
power-on
res
e
tf
low
t
hat
re
set
s
the
M
S
C7
112
and
conf
igures
various
at
tr
ibut
es
of
t
he
M
S
C
7112.
O
n
P
O
R
ESE
T
,t
he
ent
ire
M
S
C7112
device
is
re
set
.SP
LL
and
DLL
st
at
es
are
reset
,
H
R
ES
ET
is
driven,
the
SC1400
ext
ended
c
o
re
i
s
res
e
t,
and
sy
st
em
conf
igur
at
ion
is
s
a
mpled.
T
h
e
s
yst
em
is
conf
igur
ed
only
when
PO
RE
SE
T
is
as
sert
ed.
E
x
te
rnal
Ha
rd
re
s
e
t(
HRE
S
E
T
)
Input
/
O
u
tput
In
it
iat
e
s
t
he
hard
reset
flow
that
conf
igures
various
at
tr
ibut
es
of
t
he
MS
C7112.
W
h
ile
HR
ESE
T
is
a
ssert
ed,
H
R
E
SE
T
is
a
n
open-d
rain
out
put
.U
pon
hard
res
e
t,HRE
SE
T
is
driven
and
the
S
C
1400
e
x
tend
ed
co
re
is
reset
.
So
ftw
a
re
w
a
tc
hd
og
res
e
t
In
te
rnal
W
hen
t
he
M
S
C7112
wat
c
hdog
count
reac
hes
zero,
a
sof
twa
re
wat
c
hdog
res
e
t
is
s
igna
lled.
T
he
e
nabl
e
d
sof
tw
are
w
at
c
hd
og
eve
nt
then
gener
at
es
an
int
e
rnal
har
d
res
e
t
sequenc
e.
B
u
s
monit
o
r
re
set
In
te
rnal
W
hen
the
M
S
C7112
bus
mon
ito
rcount
reac
hes
zero,
a
bus
monit
o
r
h
a
rd
re
set
is
asser
ted.
T
he
e
nabl
e
d
bus
m
oni
to
r
event
t
hen
gen
erat
es
an
int
e
rn
al
hard
reset
s
equence.
JT
AG
EX
TE
ST
,
C
L
AM
P,
or
H
IG
H
Z
comm
and
In
te
rnal
W
hen
a
T
e
st
A
cces
s
P
o
rt
(T
AP
)ex
ecut
es
an
EX
T
E
ST
,CLAM
P,
or
HI
G
H
Z
comm
and,
t
h
e
T
A
P
logic
a
ssert
s
an
int
e
rnal
r
e
set
signal
that
gener
at
es
an
int
e
rnal
sof
t
reset
s
equence.
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: MSC711XADS
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