参数资料
型号: MSC7112VM800
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 数字信号处理
英文描述: 32-BIT, 200 MHz, OTHER DSP, PBGA400
封装: 17 X 17 MM, LEAD FREE, BGA-400
文件页数: 18/56页
文件大小: 1489K
代理商: MSC7112VM800
Spe
c
ific
ation
s
M
SC7
1
2
Low-Cos
t1
6
-bit
DSP
with
DDR
Control
le
rDa
ta
She
e
t,
Re
v
.1
1
Fr
ees
ca
le
Sem
ic
ond
uc
tor
25
2.5.4.
2
DDR
DR
AM
Output
AC
T
imin
g
Speci
fications
Ta
d
Ta
t
th
eou
tput
AC
ti
m
ing
s
p
ecification
s
and
m
eas
u
remen
t
cond
itio
ns
for
the
DDR
DR
AM
interface.
T
a
ble
1
9
.DDR
D
RAM
Output
A
C
T
imi
n
g
N
o
.
P
ar
a
m
et
e
r
S
y
m
b
ol
Min
Ma
x
U
n
it
Ma
sk
S
e
t
1L
4
4X
Ma
sk
S
e
t
1M
88B
200
CK
c
y
c
le
ti
m
e
,(CK
/CK
cr
o
s
si
n
g
)
1
100
M
H
z
(DDR20
0
)
133
M
H
z
(DDR26
6
)
tCK
10
Not
applicable
1.
0
7.
52
ns
204
An/
R
AS
/C
A
S
/WE
/C
KE
out
put
set
up
w
ith
r
e
spect
to
CK
tDD
KH
AS
0.
5
×
t
CK
2250
0.
5
×
t
CK
1000
ps
205
An/
R
AS
/C
A
S
/WE
/C
KE
out
put
hold
w
ith
r
e
spect
t
o
CK
tDD
KH
AX
0.
5
×
t
CK
1250
0.
5
×
t
CK
1000
ps
206
C
Sn
out
put
set
up
wit
h
res
pect
t
o
CK
tDD
KH
CS
0.
5
×
t
CK
2250
0.
5
×
t
CK
1000
ps
207
C
Sn
out
put
hold
wit
h
res
pect
t
o
CK
tDD
KH
CX
0.
5
×
t
CK
1250
0.
5
×
t
CK
1000
ps
208
CK
t
o
DQS
n
2
tDD
KH
MH
–600
600
ps
209
Dn/
D
Q
M
n
o
ut
put
s
et
up
wit
h
respec
tt
o
DQ
Sn
3
tDD
KH
DS
,
tDD
KL
DS
0.
25
×
t
MC
K
1050
0.
25
×
t
CK
750
ps
210
Dn/
D
Q
M
n
o
ut
put
hold
wit
h
respec
tt
o
DQ
Sn
3
tDD
KH
DX
,
tDD
KL
DX
0.
25
×
tCK
1050
0.
25
×
tCK
750
ps
211
DQ
Sn
pream
bl
e
st
art
4
tDD
KH
MP
–0.
25
×
t
CK
–0.
25
×
t
CK
—p
s
212
DQ
Sn
epil
og
ue
end
5
tDD
KH
ME
–600
600
ps
No
tes:
1.
A
llCK
/C
K
re
fe
re
nced
measur
ement
s
are
m
ade
f
rom
the
cross
ing
of
the
tw
o
signals
±
0
.1
V.
2.
tDD
KH
MH
can
be
m
odif
ied
t
hrough
the
T
CF
G
2[
W
RDD]
DQS
S
overr
ide
bi
ts
.T
he
DRA
M
requires
t
hat
t
he
f
irs
twrit
e
dat
a
strobe
arrives
75–125%
of
a
DRA
M
cyc
le
af
te
r
the
writ
e
com
m
a
nd
is
issued.
A
n
y
skew
bet
ween
D
Q
S
n
an
d
CK
m
u
st
be
considere
d
when
t
ry
ing
t
o
ach
iev
e
this
75
%–125%
goal.
T
he
T
C
F
G
2[
W
RDD]
bit
s
c
an
be
used
t
o
shif
tDQ
Sn
by
1/
4
DRAM
cycle
increm
ent
s
.T
he
s
k
ew
in
t
h
is
cas
e
ref
e
rs
t
o
an
int
e
rnal
skew
exist
ing
at
t
he
s
ignal
c
onnect
ions.
By
def
ault
,t
he
CK
/C
K
cros
sing
occu
rs
i
n
t
h
e
m
iddle
of
t
h
e
cont
rol
signal
(A
n/
RA
S
/CA
S
/W
E
/C
K
E
)
te
nure.
Set
ting
T
C
F
G
2[
ACS
M
]bit
s
h
ift
s
t
he
c
ont
ro
l
signal
asse
rt
ion
1/
2
DRAM
c
ycle
earlier
than
t
he
def
ault
timing.
T
h
is
m
eans
t
h
at
t
he
signal
is
ass
e
rt
ed
no
earlier
t
han
4
10
ps
bef
ore
the
C
K
/C
K
cr
ossing
and
no
l
a
te
rt
han
677
ps
af
te
rt
he
cros
sing
t
im
e
;t
he
dev
ic
e
uses
1087
ps
of
t
he
skew
bud
get
(t
he
int
e
rval
fr
om
–410
to
+677
ps)
.T
im
ing
is
verif
ied
by
refer
encing
t
he
f
alling
edge
of
CK
.S
ee
Chapter
10
of
the
M
S
C711x
Ref
erenc
e
Manual
f
or
det
ail
s
.
3.
Det
e
rmined
by
maxim
u
m
poss
ible
skew
bet
ween
a
dat
a
s
trobe
(DQ
S
)
and
any
corr
esponding
bi
t
of
d
a
ta
.
T
he
dat
a
st
robe
should
be
c
ent
ered
inside
of
t
he
dat
a
eye.
4.
Please
not
e
t
hat
th
is
spec
is
in
r
e
fe
renc
e
t
o
t
he
DQ
S
n
first
ris
in
g
edge.
Itcould
also
be
ref
e
renced
fr
om
CK(
r),
but
due
t
o
program
mable
delay
of
t
he
writ
e
strobes
(T
CF
G2[
W
RDD]),
ther
e
pre-am
bl
e
ma
y
be
extended
f
o
ra
f
u
ll
DRA
M
cy
cle.
F
o
r
this
reason,
we
ref
e
renc
e
f
rom
DQ
Sn.
5.
All
out
put
s
ar
e
ref
erenc
ed
t
o
t
he
r
is
ing
edge
of
CK
.
Not
e
that
th
is
es
sent
ia
lly
th
e
CK
/D
Q
S
n
sk
ew
in
spec
208.
I
n
addit
ion
ther
e
is
no
r
eal
“m
aximum
time
f
o
rt
he
e
p
ilogue
end.
JE
DEC
does
not
require
t
h
is
as
a
dev
ice
limit
at
ion,
but
s
imply
for
t
he
chip
to
guarant
ee
f
a
st
enough
writ
e
t
o
read
t
u
rn-around
tim
e
s.
T
h
is
i
s
already
guar
ant
eed
by
t
he
mem
o
ry
cont
roller
operat
ion.
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: MSC711XADS
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