参数资料
型号: MSC8122TMP4800V
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 数字信号处理
英文描述: 32-BIT, 300 MHz, OTHER DSP, PBGA431
封装: FCBGA-431
文件页数: 6/48页
文件大小: 1158K
代理商: MSC8122TMP4800V
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Electrical Characteristics
Freescale Semiconductor
14
2.2
Recommended Operating Conditions
Table 3 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed.
Table 4 describes thermal characteristics of the MSC8122 for the FC-PBGA packages.
Section 3.5, Thermal Considerations provides a detailed explanation of these characteristics.
Table 3. Recommended Operating Conditions
Rating
Symbol
Value
Unit
Core and PLL supply voltage:
Standard
— 400 MHz
— 500 MHz
Reduced (300 and 400 MHz)
VDD
VCCSYN
1.14 to 1.26
1.16 to 1.24
1.07 to 1.13
V
I/O supply voltage
VDDH
3.135 to 3.465
V
Input voltage
VIN
–0.2 to VDDH+0.2
V
Operating temperature range:
Standard
Extended
TJ
0 to 90
–40 to 105
°C
Table 4. Thermal Characteristics for the MSC8122
Characteristic
Symbol
FC-PBGA
20
× 20 mm5
Unit
Natural
Convection
200 ft/min
(1 m/s) airflow
Junction-to-ambient1, 2
RθJA
26
21
°C/W
Junction-to-ambient, four-layer board1, 3
RθJA
19
15
°C/W
Junction-to-board (bottom)4
RθJB
9
°C/W
Junction-to-case5
RθJC
0.9
°C/W
Junction-to-package-top6
ΨJT
1
°C/W
Notes:
1.
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2.
Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
3.
Per JEDEC JESD51-6 with the board horizontal.
4.
Thermal resistance between the die and the printed circuit board per JEDEC JESD 51-8. Board temperature is measured on
the top surface of the board near the package.
5.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
6.
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2.
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