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MSM66573 Family User's Manual
Chapter 13 A/D Converter Functions
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A/D interrupt control register (ADINT0)
ADINT0 is a 4-bit register that mainly controls the generation of interrupt requests by the
A/D converter.
ADINT0 can be read from and written to by the program. However, write operations are
invalid for bits 4 through 7. If read, a value of "1" will always be obtained for bits 4 through
7.
When reset (
RES signal input, execution of a BRK instruction, overflow of the watchdog
timer, opcode trap), ADINT0 becomes F0H.
Figure 13-4 shows the ADINT0 configuration.
[Description of each bit]
INTSN0 (bit 0)
INTSN0 indicates whether one cycle of the scan channels has been completed.
When INTSN0 is "0", then "one cycle is not complete". If "1", then "one cycle is complete".
Here, "one cycle is complete" signifies that in the scan mode, A/D conversion of channel
7 is complete. INTSN0 must be reset to "0” by the program.
INTST0 (bit 1)
INTST0 indicates whether A/D conversion in the select mode is complete.
When INTST0 is "1", then A/D conversion is complete. INTST0 must be reset to "0" by
the program.
ADSNIE0 (bit 2)
ADSNIE0 enables or disables interrupt requests when one cycle of scan channels is
complete. Here, "one cycle is complete" signifies that in the scan mode, A/D conversion
of channel 7 is complete.
ADSTIE0 (bit 3)
ADSTIE0 enables or disables interrupt requests when A/D conversion is completed in the
select mode.
7
—
6
—
5
—
4
—
3
ADSTIE0
2
1
0
1
One cycle of scan channels is not complete
One cycle of scan channels is complete
ADSNIE0 INTST0 INTSN0
0
1
A/D conversion in select mode is not complete
A/D conversion in select mode is complete
0
1
Disable interrupts from INTSN0
Enable interrupts from INTSN0
0
1
Disable interrupts from INTST0
Enable interrupts from INTST0
11110000
ADINT0
At reset
Address:
R/W access:
009E [H]
R/W
"—" indicates a nonexistent bit.
When read, its value will be "1."
Figure 13-4 ADINT0 Configuration