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参数资料
| 型号： | MSM8129W-35 |
| 元件分类： | SRAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 35 ns, CQCC32 |
| 封装： | CERAMIC, LCC-32 |
| 文件页数： | 6/9页 |
| 文件大小： | 74K |
| 代理商： | MSM8129W-35 |
ISSUE 2.0 April 2001
MSM8129 - 020/025/30
6
Write Cycle No.2 Timing Waveform (5)
CS
tWR(2)
tCW (4)
(6)
t AW
tWC
Address
t
WP(1)
DW
tDH
WE
D0~7 out
D0~7 in
WHZ(3,9)
t AS(3)
t OW
tOH
(7)
(8)
High-Z
AC Characteristics Notes
(1) A write occurs during the overlap (t
WP) of a low CS and a low WE.
(2) t
WR is measured from the earlier of CS or WE going high to the end of write cycle.
(3) During this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(4) If the CS low transition occurs simultaneously with the WE low transition or after the WE low transition, outputs
remain in a high impedance state.
(5) OE is continuously low. (OE=V
IL)
(6) D
OUT is in the same phase as written data of this write cycle.
(7) D
OUT is the read data of next address.
(8) If CS is low during this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(9) t
WHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not
referenced to output voltage levels. These parameters are sampled and not 100% tested.
Low V
CC Data Retention Timing Waveform
t R
tCDR
4.5V
2.2V
4.5V
2.2V
0V
DATA RETENTION MODE
Vcc
CS
V DR
CS>Vcc-0.2V
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