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参数资料
| 型号： | MSM82C37B-5RS |
| 厂商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | Programmable DMA Controller(可编程DMA控制器) |
| 中文描述： | 可编程DMA控制器（可编程DMA的控制器） |
| 文件页数： | 15/33页 |
| 文件大小： | 209K |
| 代理商： | MSM82C37B-5RS |
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15/33
Semiconductor
MSM82C37B-5RS/GS/VJS
OUTLINE OF FUNCTIONS
The MSM82C37B-5 consists of five blocks = three logic sections, an internal register section, and
a counter section.
The logic sections include a timing control block where the internal timing and external control
signals are generated, a command control block where each instruction from the CPU is
decoded, and a priority decision block where the order of DMA channel priority is determined.
The purpose of the internal register section is to hold internal states and instructions from the
CPU, while the counter section computes addresses and word counts.
DESCRIPTION OF OPERATIONS
The MSM82C37B-5 operates in two cycles (called the idle and active cycles) which are divided
into independent states. Each state is commenced by a clock falling edge and continues for a
single clock cycle. The transition from one state to the next in DMA operations is outlined in
Figure 1.
IDLE CYCLE
The idle cycle is entered from the Sl state when there is no valid DMA request on any
MSM82C37B-5 channel. During this cycle, DREQ and
CS
inputs are monitored during each
cycle. When a valid DMA request is then received, an active cycle is commenced. And if the
HLDA and
CS
inputs are at low level, a programming state is started with MSM82C37B-5
reading or writing executed by
IOR
or
IOW
. Programming details are described later.
ACTIVE CYCLE
If a DMA request is received in an unmasked channel while the MSM82C37B-5 is in idle cycle,
or if a software DREQ is generated, the HRQ is changed to high level to commence an active
cycle. The initial state of an active cycle is the S
0
state which is repeated until the HLDA input
from the CPU is changed to high level. (But because of internal operational reasons, a minimum
of one clock cycle is required for the HLDA is be changed to high level by the CPU after the HRQ
has become high level. That is, the S
0
state must be repeated at least twice.)
After the HLDA has been changed to high level, the S
0
state proceeds to operational states S1
thru S
4
during I/O-memory transfers, or to operational states S
11
thru S
14
and S
21
thru S
24
during memory-memory transfers.
If the memory or I/O device cannot be accessed within the normal timing, an SW state (wait
state) can be inserted by a READY input to extend the timing.
相关PDF资料 |
PDF描述 |
|---|---|
| MSM82C37B-5VJS | Programmable DMA Controller(可编程DMA控制器) |
| MSM82C51A-2(中文) | Universal Synchronous Asynchronous Receiver Transmitter(通用同步/异步接收发送器,同步通讯最高可达64Kbps,异步通讯最高可达38.4Kbps) |
| MSM82C51A-2 | Universal Synchronous Asynchronous Receiver Transmitter(通用同步/异步接收发送器,同步通讯最高可达64Kbps,异步通讯最高可达38.4Kbps) |
| MSM82C53-2 | Programmable Universal Timers(可编程中断定时器,最高计数频率8MHz) |
| MSM82C54-2 | Programmable Universal Timers(可编程中断定时器,最高计数频率10MHz) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MSM82C37B-5VJS | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:PROGRAMMABLE DMA CONTROLLER |
| MSM82C43 | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:INPUT/OUTPUT PORT EXPANDER |
| MSM82C51A-2GS | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER |
| MSM82C51A-2GS-K | 制造商:OK International 功能描述:USART, 32 Pin, Plastic, SOP 制造商:OKI Semiconductor 功能描述:USART, 32 Pin, Plastic, SOP |
| MSM82C51A-2JS | 制造商:ROHM Semiconductor 功能描述: |
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