- 您现在的位置：买卖IC网 > PDF目录299521 > MSM82C54-2RS (OKI SEMICONDUCTOR CO., LTD.) CMOS PROGRAMMABLE INTERVAL TIMER PDF资料下载
参数资料
| 型号： | MSM82C54-2RS |
| 厂商： | OKI SEMICONDUCTOR CO., LTD. |
| 元件分类： | 定时器 |
| 英文描述： | CMOS PROGRAMMABLE INTERVAL TIMER |
| 中文描述： | CMOS可编程间隔计时器 |
| 文件页数： | 5/23页 |
| 文件大小： | 161K |
| 代理商： | MSM82C54-2RS |
13/23
Semiconductor
MSM82C54-2RS/GS/JS
Mode 2
Application: Rate generator, real-time interrupt clock.
Output operation: The output is set to “H” level by control word setting. When the initial
count value is decremented to 1, the output is set to “L” level during one clock pulse, and is
then set to “H” level again. The initial count value is reloaded, and the above sequence
repeats. In mode 2, the same sequence is repeated at intervals of N clock pulses if the initial
count value is N for example.
Gate function: “H” level validates counting, and “L” level invalidates it. If the gate signal is
set to “L” level when the output pulse is “L” level, the output is immediately set to “H” level.
At the falling edge of the clock pulse succeeding the trigger, the count value is reloaded and
counting starts. The gate input can be used for counter synchronization in this way.
Count value load timing:
After the control word and initial count value is written, the count value is loaded to the CE
at the falling edge of the next clock pulse. The output is set to “L” level upon lapse of N clock
pulses after writing the initial count value N. Counter synchronization By software is possible
in this way.
Count value writing during counting:
Count value writing does not affect the current counting operation sequence. If new count
value writing completes and the gate trigger arrives before the end of current counting
operation, the count value is loaded to the CE at the falling edge of next clock pulse and
counting continues from the new count value. If no gate trigger arrives, the new count value
is loaded to the CE at the end of the current counting operation cycle. In mode 2, count value
of 1 is prohibited.
Mode 3
Application: Baud rate generator, square wave generator
Output operation: Same as mode 2 except that the output duty is different.
The output is set to “H” level by control word setting. When the count becomes half the initial
count value, the output is set to “L” level and kept at “L” level during the remainder of the
count. Mode 3 repeats the above sequence periodically. If the initial count value is N, the
output becomes a square wave with a period of N.
Gate operation: “H” level validates counting, and “L” level invalidates it. If the gate signal
is set to “L” level when the output is “L” level, the output is immediately set to “H” level. The
initial count value is reloaded at the falling edge of the clock pulse succeeding the next gate
trigger. The gate can be used for counter synchronization in this way.
Count value load timing:
After the control word and initial count value are written, the count value is loaded to the CE
at the falling edge of the next clock pulse, Counter synchronization by software is possible
in this way.
Count value writing during counting:
The count value writing does not affect the current counting operation. When the gate trigger
input arrives before the end of a half cycle of the square wave after writing the new count
value, the new count value is loaded in the CE at the falling edge of the next clock pulse, and
counting continues using the new count value. If there is no gate trigger, the new count value
is loaded at the end of the half cycle and counting continues.
Even number counting operation:
The output is initially set to “H” level. The initial count value is loaded to the CE at the falling
edge of the next clock pulse, and is decremented by 2 by consecutive clock pulses. When the
counter value becomes 2, the output is set to “L” level, the initial value is reloaded and then
the above operation is repeated.
相关PDF资料 |
PDF描述 |
|---|---|
| MSM832JLM-025 | 32K X 8 STANDARD SRAM, 25 ns, CQCC32 |
| MSM832TMB-10 | 32K X 8 STANDARD SRAM, 100 ns, CDIP28 |
| MSM9201-01 | Fluorescent Display Tube Controller Driver |
| MSM9223 | 27-Bit Duplex/Triplex VFD Controller/Driver with Digital Dimming, ADC and Keyscan |
| MSM9225 | CAN (Controller Area Network) Controller |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MSM82C55A | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CMOS PROGRAMMABLE PERIPHERAL INTERFACE |
| MSM82C55A-2G3-2K | 制造商:OKI Semiconductor 功能描述:MSM82C55A-2G3-2K CPU I/O EOL211209 |
| MSM82C55A-2GS | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:CMOS PROGRAMMABLE PERIPHERAL INTERFACE |
| MSM82C55A-2GS-2K | 制造商:ROHM Semiconductor 功能描述: 制造商:ROHM Semiconductor 功能描述:CMOS PROGRAMMABLE PERIPHERAL INTERFACE |
| MSM82C55A-2R3 | 制造商:OKI Semiconductor 功能描述:CPU I/O EOL211209 制造商:ROHM Semiconductor 功能描述: |
发布紧急采购，3分钟左右您将得到回复。