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参数资料
| 型号： | MSM82C55A_2 |
| 厂商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | Programmable Universal I/O Interface Device(可编程通用I/O接口器件) |
| 中文描述： | 可编程通用I / O接口设备（可编程通用的I / O接口器件） |
| 文件页数： | 13/26页 |
| 文件大小： | 168K |
| 代理商： | MSM82C55A_2 |
13/26
Semiconductor
MSM82C55A-2RS/GS/VJS
1
1
1
1
1
D
7
1
1
1
1
2
3
4
5
1
Type
6
7
8
9
1
1
1
1
1
1
1
0
0
0
0
0
D
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D
4
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
0
D
3
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
D
2
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
D
1
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
0
D
0
1
0
1
0
1
0
1
0
1
0
1
Output
Output
Output
Output
Output
Port A
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Input
Output
High Order 4 Bits
of Port C
Input
Input
Input
Output
Output
Output
Output
Input
Input
Input
Input
Output
Input
Input
Output
Output
Port B
Output
Input
Input
Output
Output
Input
Input
Output
Output
Input
Input
Input
Output
Input
Output
Output
Control Word
Group A
Group B
Low Order 4 Bits
of Port C
Input
Ouput
Input
Output
Input
Output
Input
Output
Input
Output
Input
10
11
12
13
14
15
16
Notes: When used in mode 0 for both groups A and B
2. Mode 1 (Strobe input/output operation)
In mode 1, the strobe, interrupt and other control signals are used when input/output
operations are made from a specified port. This mode is available for both groups A and
B. In group A at this time, port A is used as the data line and port C as the control signal.
Following is a description of the input operation in mode 1.
STB
(Strobe input)
When this signal is low level, the data output from terminal to port is fetched into the
internal latch of the port. This can be made independent from the CPU, and the data is not
output to the data bus until the RD signal arrives from the CPU.
IBF (Input buffer full flag output)
This is the response signal for the
STB
. This signal when turned to high level indicates that
data is fetched into the input latch. This signal turns to high level at the falling edge of
STB
and to low level at the rising edge of
RD
.
INTR (Interrupt request output)
This is the interrupt request signal for the CPU of the data fetched into the input latch. It
is indicated by high level only when the internal INTE flip-flop is set. This signal turns to
high level at the rising edge of the
STB
(IBF = 1 at this time) and low level at the falling edge
of the
RD
when the INTE is set.
INTE
A
of group A is set when the bit for PC
4
is set, while INTE
B
of group B is set when the
bit for PC
2
is set.
Following is a description of the output operation of mode 1.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MSM82C55A-2G3-2K | 制造商:OKI Semiconductor 功能描述:MSM82C55A-2G3-2K CPU I/O EOL211209 |
| MSM82C55A-2GS | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:CMOS PROGRAMMABLE PERIPHERAL INTERFACE |
| MSM82C55A-2GS-2K | 制造商:ROHM Semiconductor 功能描述: 制造商:ROHM Semiconductor 功能描述:CMOS PROGRAMMABLE PERIPHERAL INTERFACE |
| MSM82C55A-2R3 | 制造商:OKI Semiconductor 功能描述:CPU I/O EOL211209 制造商:ROHM Semiconductor 功能描述: |
| MSM82C55A-2RS | 制造商:ROHM Semiconductor 功能描述: 制造商:OKI Semiconductor 功能描述:PERIPHERAL INTERFACE, 40 Pin, Plastic, DIP 制造商:ROHM Semiconductor 功能描述:CMOS PROGRAMMABLE PERIPHERAL INTERFACE |
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