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参数资料
| 型号： | MSM82C55A_2 |
| 厂商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | Programmable Universal I/O Interface Device(可编程通用I/O接口器件) |
| 中文描述： | 可编程通用I / O接口设备（可编程通用的I / O接口器件） |
| 文件页数： | 16/26页 |
| 文件大小： | 168K |
| 代理商： | MSM82C55A_2 |
16/26
Semiconductor
MSM82C55A-2RS/GS/VJS
(b) When group A is mode 1 input and group B is mode 1 output.
￥
0
1
1/0
1
1
0
1
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Selection of I/O of PC
6
and PC
7
when not defined as a control pin.
1 = Input
0 = Output
STB
A
IBF
A
INTR
A
I/O
PC
4
PC
5
PC
3
PC
6
, PC
7
PB
7
- PB
0
PA
7
- PA
0
Group A: Mode 1 Input
Group B: Mode 1 Output
OBF
B
ACK
B
INTR
B
PC
1
PC
2
PC
0
8
RD
2
8
WR
3. Mode 2 (Strobe bidirectional bus I/O operation)
In mode 2, it is possible to transfer data in 2 directions through a single 8-bit port. This
operation is akin to a combination between input and output operations. Port C waits for
the control signal in this case, too. Mode 2 is available only for group A, however.
Next, a description is made on mode 2.
OBF
(Output buffer full flag output)
This signal when turned to low level indicates that data has been written to the internal
output latch upon receipt of the
WR
signal from the CPU. At this time, port A is still in the
high impedance status and the data is not yet output to the outside. This signal turns to low
level at the rising edge of the WR and high level at the falling edge of the
ACK
.
ACK
(Acknowledge input)
When a low level signal is input to this pin, the high impedance status of port A is cleared,
the buffer is enabled, and the data written to the internal output latch is output to port A.
When the input returns to high level, port A is made into the high impedance status.
STB
(Strobe input)
When this signal turns to low level, the data output to the port from the pin is fetched into
the internal input latch. The data is output to the data bus upon receipt of the RD signal from
the CPU, but it remains in the high impedance status until then.
IBF (Input buffer full flag output)
This signal when turned to high level indicates that data from the pin has been fetched into
the input latch. This signal turns to high level at the falling edge of the
STB
and low level
at the rising edge of the
RD
.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MSM82C55A-2G3-2K | 制造商:OKI Semiconductor 功能描述:MSM82C55A-2G3-2K CPU I/O EOL211209 |
| MSM82C55A-2GS | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:CMOS PROGRAMMABLE PERIPHERAL INTERFACE |
| MSM82C55A-2GS-2K | 制造商:ROHM Semiconductor 功能描述: 制造商:ROHM Semiconductor 功能描述:CMOS PROGRAMMABLE PERIPHERAL INTERFACE |
| MSM82C55A-2R3 | 制造商:OKI Semiconductor 功能描述:CPU I/O EOL211209 制造商:ROHM Semiconductor 功能描述: |
| MSM82C55A-2RS | 制造商:ROHM Semiconductor 功能描述: 制造商:OKI Semiconductor 功能描述:PERIPHERAL INTERFACE, 40 Pin, Plastic, DIP 制造商:ROHM Semiconductor 功能描述:CMOS PROGRAMMABLE PERIPHERAL INTERFACE |
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