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参数资料
型号： MSP430F5633IPZ
厂商： TEXAS INSTRUMENTS INC
元件分类： 微控制器/微处理器
英文描述： 16-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PQFP100
封装： GREEN, PLASTIC, LQFP-100
文件页数： 35/101页
文件大小： 1073K
代理商： MSP430F5633IPZ
PRODUCTPREVIEW
MSP430F563x
www.ti.com
SLAS650A – JUNE 2010 – REVISED JULY 2010
Recommended Operating Conditions
MIN
NOM
MAX
UNIT
PMMCOREVx = 0
1.8
3.6
Supply voltage during program execution and flash
PMMCOREVx = 0, 1
2.0
3.6
VCC
programming (AVCC1 = DVCC1 = DVCC2 = DVCC3 =
V
PMMCOREVx = 0, 1, 2
2.2
3.6
DVCC = VCC)
(1)
PMMCOREVx = 0, 1, 2, 3
2.4
3.6
PMMCOREVx = 0
1.8
3.6
Supply voltage during USB operation, USB PLL
PMMCOREVx = 0, 1
2.0
3.6
disabled
PMMCOREVx = 0, 1, 2
2.2
3.6
USB_EN = 1, UPLLEN = 0
VCC, USB
V
PMMCOREVx = 0, 1, 2, 3
2.4
3.6
Supply voltage during USB operation, USB PLL
PMMCOREVx = 2
2.2
3.6
enabled(2)
PMMCOREVx = 2, 3
2.4
3.6
USB_EN = 1, UPLLEN = 1
Supply voltage (AVSS1 = AVSS2 = AVSS3 = DVSS1 =
VSS
0
V
DVSS2 = DVSS3 = VSS)
TA = 0°C to 85°C
1.55
3.6
VBAT,RTC
Backup-supply voltage with RTC operational
V
TA = –40°C to 85°C
1.70
3.6
VBAT,MEM
Backup-supply voltage with backup memory retained.
TA = –40°C to 85°C
1.20
3.6
V
TA
Operating free-air temperature
I version
–40
85
°C
TJ
Operating junction temperature
I version
–40
85
°C
CBAK
Capacitance at pin VBAK
1
4.7
10
nF
CVCORE
Capacitor at VCORE
470
nF
CDVCC/CVCORE
Capacitor ratio of DVCC to VCORE
10
PMMCOREVx = 0,
1.8 V
≤ VCC ≤ 3.6 V
0
8.0
(default condition)
PMMCOREVx = 1, 2
0
12.0
Processor frequency (maximum MCLK frequency)(3) (4)
V
≤ VCC ≤ 3.6 V
fSYSTEM
MHz
(see Figure 1)
PMMCOREVx = 2,
0
16.0
2.2 V
≤ VCC ≤ 3.6 V
PMMCOREVx = 3,
0
20.0
2.4 V
≤ VCC ≤ 3.6 V
fSYSTEM_USB
Minimum processor frequency for USB operation
1.5
MHz
USB_wait
Wait state cycles during USB operation
16
cycles
(1)
It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
(2)
USB operation with USB PLL enabled requires PMMCOREVx
≥ 2 for proper operation.
(3)
The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
(4)
Modules may have a different maximum input clock specification. Refer to the specification of the respective module in this data sheet.
Copyright 2010, Texas Instruments Incorporated
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