参数资料
型号: MSP430P313IDLR
厂商: TEXAS INSTRUMENTS INC
元件分类: 微控制器/微处理器
英文描述: 16-BIT, OTPROM, 3.3 MHz, RISC MICROCONTROLLER, PDSO56
封装: PLASTIC, SSOP-56
文件页数: 29/31页
文件大小: 346K
代理商: MSP430P313IDLR
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D FEBRUARY 1998 REVISED APRIL 2000
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Table 2. Address Mode Descriptions
ADDRESS MODE
s
d
SYNTAX
EXAMPLE
OPERATION
Register
MOV Rs, Rd
MOV R10, R11
R10
→ R11
Indexed
MOV X(Rn), Y(Rm)
MOV 2(R5), 6(R6)
M(2 + R5)
→ M(6 + R6)
Symbolic (PC relative)
MOV EDE, TONI
M(EDE)
→ M(TONI)
Absolute
MOV &MEM, &TCDAT
M(MEM)
→ M(TCDAT)
Indirect
MOV @Rn, Y(Rm)
MOV @R10, Tab(R6)
M(R10)
→ M(Tab + R6)
Indirect autoincrement
MOV @Rn+, RM
MOV @R10+, R11
M(R10)
→ R11, R10 + 2 → R10
Immediate
MOV #X, TONI
MOV #45, TONI
#45
→ M(TONI)
NOTE: s = source
d = destination
Computed branches (BR) and subroutine call (CALL) instructions use the same addressing modes as the other
instructions. These addressing modes provide indirect addressing, ideally suited for computed branches and
calls. The full use of this programming capability permits a program structure different from conventional 8- and
16-bit controllers. For example, numerous routines can easily be designed to deal with pointers and stacks
instead of using flag type programs for flow control.
operation modes and interrupts
The MSP430 operating modes support various advanced requirements for ultra low-power and ultra-low energy
consumption. This is achieved by the management of the operations during the different module operation
modes and CPU states. The requirements are fully supported during interrupt event handling. An interrupt event
awakens the system from each of the various operating modes and returns with the RETI instruction to the mode
that was selected before the interrupt event. The clocks used are ACLK and MCLK. ACLK is the crystal
frequency and MCLK , a multiple of ACLK, is used as the system clock.
The software can configure five operating modes:
D Active mode (AM). The CPU is enabled with different combinations of active peripheral modules.
D Low-power mode 0 (LPM0). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals
are active, and loop control for MCLK is active.
D Low-power mode 1 (LPM1). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals
are active, and loop control for MCLK is inactive.
D Low-power mode 2 (LPM2). The CPU is disabled, peripheral operation continues, ACLK signal is active,
and MCLK and loop control for MCLK are inactive.
D Low-power mode 3 (LPM3). The CPU is disabled, peripheral operation continues, ACLK signal is active,
MCLK and loop control for MCLK are inactive, and the dc generator for the digital controlled oscillator (DCO)
(
MCLK generator) is switched off.
D Low-power mode 4 (LPM4). The CPU is disabled, peripheral operation continues, ACLK signal is inactive
(crystal oscillator stopped), MCLK and loop control for MCLK are inactive, and the dc generator for the DCO
is switched off.
The special function registers (SFR) include module-enable bits that stop or enable the operation of the specific
peripheral module. All registers of the peripherals may be accessed if the operational function is stopped or
enabled. However, some peripheral current-saving functions are accessed through the state of local register
bits. An example is the enable/disable of the analog voltage generator in the LCD peripheral, which is turned
on or off using one register bit.
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