参数资料
型号: MSP430P313IDLR
厂商: TEXAS INSTRUMENTS INC
元件分类: 微控制器/微处理器
英文描述: 16-BIT, OTPROM, 3.3 MHz, RISC MICROCONTROLLER, PDSO56
封装: PLASTIC, SSOP-56
文件页数: 5/31页
文件大小: 346K
代理商: MSP430P313IDLR
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D FEBRUARY 1998 REVISED APRIL 2000
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
peripherals (continued)
slope A/D conversion
Slope A/D conversion is accomplished with the timer/port module using external resistor(s) for reference (Rref),
external resistor(s) to the measured (Rmeas), and an external capacitor. The external components are driven
by software in such a way that the internal counter measures the time that is needed to charge or discharge
the capacitor. The reference resistor’s (Rref) charge or discharge time is represented by Nref counts. The
unknown resistors (Rmeas) charge or discharge time is represented by Nmeas counts. The unknown resistor’s
value (Rmeas) is the value of Rref multiplied by the relative number of counts (Nmeas/Nref). This value determines
resistive sensor values that correspond to the physical data, for example temperature, when an NTC or PTC
resistor is used.
Basic Timer1
The Basic Timer1 (BT1) divides the frequency of MCLK or ACLK, as selected with the SSEL bit, to provide low
frequency control signals. This is done within the system by one central divider, the basic timer1, to support low
current applications. The BTCTL control register contains the flags which controls or selects the different
operational functions. When the supply voltage is applied or when a reset of the device (RST/NMI pin), a
watchdog overflow, or a watchdog security key violation occurs, all bits in the register hold undefined or
unchanged status. The user software usually configures the operational conditions on the BT1 during
initialization.
The Basic Timer1 has two 8 bit timers which can be cascaded to a 16 bit timer. Both timers can be read and
written by software. Two bits in the SFR address range handle the system control interaction according to the
function implemented in the Basic Timer1. These two bits are the Basic Timer1 interrupt flag (BTIFG) and the
basic timer interrupt enable (BTIE) bit.
Watchdog Timer
The primary function of the Watchdog Timer (WDT) module is to perform a controlled system restart after a
software problem has occurred. If the selected time interval expires, a system reset is generated. If this
watchdog function is not needed in an application, the module can work as an interval timer, which generates
an interrupt after the selected time interval.
The Watchdog Timer counter (WDTCNT) is a 15/16-bit up-counter which is not directly accessible by software.
The WDTCNT is controlled using the Watchdog Timer control register (WDTCTL), which is a 16-bit read/write
register. Writing to WDTCTL, in both operating modes (watchdog or timer) is only possible by using the correct
password in the high-byte. The low-byte stores data written to the WDTCTL. The high-byte password is 05Ah.
If any value other than 05Ah is written to the high-byte of the WDTCTL, a system reset PUC is generated. When
the password is read its value is 069h. This minimizes accidental write operations to the WDTCTL register. In
addition to the Watchdog Timer control bits, there are two bits included in the WDTCTL which configure the NMI
pin.
8-Bit Timer/Counter
The 8-bit interval timer supports three major functions for the application:
Serial communication or data exchange
Pulse counting or pulse accumulation
Timer
The 8-bit Timer/Counter peripheral includes the following major blocks: an 8-bit up-counter with
preload-register, an 8-bit control register, an input clock selector, an edge detection (e.g. start bit detection for
asynchronous protocols), and an input and output data latch, triggered by the carry-out-signal from the 8-bit
counter.
The 8-bit counter counts up with an input clock, which is selected by two control bits from the control register.
The four possible clock sources are MCLK, ACLK, the external signal from terminal P0.1, and the signal from
the logical AND of MCLK and terminal P0.1.
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