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参数资料
| 型号： | MSX340-10PB480 |
| 元件分类： | 数字信号处理外设 |
| 英文描述： | DSP-CROSSBAR SWITCH, PBGA480 |
| 封装： | BGA-480 |
| 文件页数： | 4/61页 |
| 文件大小： | 1443K |
| 代理商： | MSX340-10PB480 |
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MSX Family Data Sheet
12
[Rev. 1.8] 2/28/01
I-Cube, Inc.
Most of the signals on the MSX device’s RC interface are bi-directional. These signals receive
data during write operations. During read operations these pins receive data during the first part of
the cycle, and then drive the interface in the final part of the cycle. RCA[9:0], RCB[9:0], and
RCC[0] are bi-directional pins. RCC[3:1], RC_CLK, RC_EN#, and RCI[1:0] are dedicated inputs.
RC_RDY is a dedicated output.
The RC_CLK signal is the strobe that latches write data into the MSX device. It synchronizes the
signals driven on to the RC interface and determines the rate at which commands can be loaded
into the MSX device. The MSX device latches command data on the falling edge of RC_CLK
when RC_EN# is asserted. RC Write operations can be repeated on consecutive clocks simply by
keeping the RC_EN# signal asserted and providing new commands on the RCA, RCB, RCC, and
RCI signals. RC Read operations require four cycles and cannot be performed on back-to-back
clocks.
RC_EN# is an active low signal that indicates the beginning of an RC operation. Back-to-back
RC Write operations may be performed by keeping the RC_EN# signal asserted. During RC Read
operations RC_EN# must remain asserted until the cycle is complete. Back-to-back RC Read
operations can be executed simply by keeping RC_EN# asserted.
The MSX device asserts RC_RDY when it has entered the final stage of a read. RC_RDY is
asserted on the falling edge of RC_CLK, and de-asserted on the next falling edge. The MSX
device will be driving valid read data on the RC interface when RC_RDY is asserted high.
.
Figure 4
MSX Switch Configuration Signals
TMS
TDI
TCK
TRST#
TDO
RapidConfigure
J
T
A
G
UPDATE
RCE
2
10
RCA[9:0]
RCB[9:0]
RCC[0]
RCC[3:1]
RCI[1:0]
RC_EN#
RC_CLK
RC_RDY
3
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