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参数资料
| 型号： | MT28F320J3RG-11FET |
| 元件分类： | PROM |
| 英文描述： | 2M X 16 FLASH 2.7V PROM, 110 ns, PDSO56 |
| 封装： | TSOP1-56 |
| 文件页数： | 51/52页 |
| 文件大小： | 564K |
| 代理商： | MT28F320J3RG-11FET |
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8
128Mb, 64Mb, 32Mb Q-Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F640J3_8.p65 – Rev. 7, Pub. 11/02
2002, Micron Technology, Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
Figure 1
Memory Map
Table 2
Chip Enable Truth Table
CE2
CE1
CE0
DEVICE
VIL
Enabled
VIL
VIH
Disabled
VIL
VIH
VIL
Disabled
VIL
VIH
Disabled
VIH
VIL
Enabled
VIH
VIL
VIH
Enabled
VIH
VIL
Enabled
VIH
Disabled
NOTE: For single-chip applications, CE2 and CE1 can be
connected to GND.
128KB Block
31
128KB Block
1
128KB Block
0
64K-Word Block
63
64K-Word Block
31
64K-Word Block
1
64K-Word Block
0
7FFFFFh
7E0000h
3FFFFFh
3E0000h
03FFFFh
020000h
01FFFFh
000000h
3FFFFFh
3F0000h
1FFFFFh
1F0000h
01FFFFh
010000h
00FFFFh
000000h
32M
b
64Mb
128Mb
Byte-Wide (x8) Mode
Word-Wide (x16) Mode
A0–A23: 128Mb
A0–A22: 64Mb
A0–A21: 32Mb
A1–A23: 128Mb
A1–A22: 64Mb
A1–A21: 32Mb
128KB Block
63
64K-Word Block
127
FFFFFFh
FE0000h
7FFFFFh
7F0000h
128KB Block
127
MEMORY ARCHITECTURE
The MT28F128J3, MT28F640J3, and MT28F320J3
memory array architecture is divided into one hun-
dred twenty-eight, sixty-four, or thirty-two 128KB
blocks, respectively (see Figure 1). The internal archi-
tecture allows greater flexibility when updating data
because individual code portions can be updated in-
dependently of the rest of the code.
high-speed page buffer. A0–A2 select data in the page
buffer. Asynchronous page mode, with a page size of
four words or eight bytes, is supported with no addi-
tional commands required.
OUTPUT DISABLE
The device outputs are disabled with OE# at a logic
HIGH level (VIH). Output pins DQ0–DQ15 are placed in
High-Z.
STANDBY
CE0, CE1, and CE2 can disable the device (see
Table 2) and place it in standby mode, which substan-
tially reduces device power consumption. DQ0–DQ15
outputs are placed in High-Z, independent of OE#. If
deselected during block erase, program, or lock bit con-
figuration, the ISM continues functioning and consum-
ing active power until the operation completes.
RESET/POWER-DOWN
RP# puts the device into the reset/power-down
mode when set to VIL.
During read, RP# LOW deselects the memory, places
output drivers in High-Z, and turns off internal cir-
cuitry. RP# must be held LOW for a minimum of tPLPH.
tRWH is required after return from reset mode until
initial memory access outputs are valid. After this wake-
up interval, normal operation is restored. The com-
mand execution logic (CEL) is reset to the read array
mode and the status register is set to 80h.
During block erase, program, or lock bit configura-
tion, RP# LOW aborts the operation. In default mode,
STS transitions LOW and remains LOW for a maximum
time of tPLPH + tPHRH, until the RESET operation is
complete. Any memory content changes are no longer
BUS OPERATION
All bus cycles to and from the Flash memory must
conform to the standard microprocessor bus cycles.
The local CPU reads and writes Flash memory in-
system.
READ
Information can be read from any block, query, iden-
tifier codes, or status register, regardless of the VPEN
voltage. The device automatically resets to read array
mode upon initial device power-up or after exit from
reset/power-down mode. To access other read mode
commands (READ ARRAY, READ QUERY, READ IDEN-
TIFIER CODES, or READ STATUS REGISTER), these
commands should be issued to the CUI. Six control
pins dictate the data flow in and out of the device: CE0,
CE1, CE2, OE#, WE#, and RP#. In system designs using
multiple Q-Flash devices, CE0, CE1, and CE2 (CEx)
select the memory device (see Table 2). To drive data
out of the device and onto the I/O bus, OE# must be
active and WE# must be inactive (VIH).
When reading information in read array mode, the
device defaults to asynchronous page mode, thus pro-
viding a high data transfer rate for memory subsystems.
In this state, data is internally read and stored in a
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT28F320J3RG-12 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:Q-FLASHTM MEMORY |
| MT28F320J3RG-12ET | 制造商:MICRON 制造商全称:Micron Technology 功能描述:Q-FLASHTM MEMORY |
| MT28F320J3RG-15 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:Q-FLASHTM MEMORY |
| MT28F320J3RG-15ET | 制造商:MICRON 制造商全称:Micron Technology 功能描述:Q-FLASHTM MEMORY |
| MT28F320J3RP-11 ET TR | 功能描述:IC FLASH 32MBIT 110NS 56TSOP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:378 系列:- 格式 - 存储器:闪存 存储器类型:FLASH 存储容量:8M（1M x 8，512K x 16） 速度:110ns 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-CBGA 供应商设备封装:48-CBGA（7x7） 包装:托盘 |
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