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参数资料
| 型号： | MT42L64M64D2MC-3 IT:A |
| 厂商： | Micron Technology Inc |
| 文件页数： | 4/164页 |
| 文件大小： | 0K |
| 描述： | IC DDR2 SDRAM 2GBIT 240FBGA |
| 标准包装： | 1,000 |
| 格式 - 存储器： | RAM |
| 存储器类型： | 移动 LPDDR2 SDRAM |
| 存储容量： | 4G（64M x 64） |
| 速度： | 333MHz |
| 接口： | 并联 |
| 电源电压： | 1.14 V ~ 1.3 V |
| 工作温度： | -25°C ~ 85°C |
| 封装/外壳： | 240-WFBGA |
| 供应商设备封装： | 240-FBGA（14x14） |
| 包装： | 散装 |
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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
Contents
General Description ....................................................................................................................................... 11
General Notes ............................................................................................................................................ 11
I DD Specifications ........................................................................................................................................... 12
Package Block Diagrams ................................................................................................................................. 16
Package Dimensions ....................................................................................................................................... 23
Ball Assignments and Descriptions ................................................................................................................. 33
Functional Description ................................................................................................................................... 39
Power-Up ....................................................................................................................................................... 40
Initialization After RESET (Without Voltage Ramp) ...................................................................................... 42
Power-Off ....................................................................................................................................................... 42
Uncontrolled Power-Off .............................................................................................................................. 43
Mode Register Definition ................................................................................................................................ 43
Mode Register Assignments and Definitions ................................................................................................ 43
ACTIVATE Command ..................................................................................................................................... 54
8-Bank Device Operation ............................................................................................................................ 54
Read and Write Access Modes ......................................................................................................................... 55
Burst READ Command ................................................................................................................................... 55
READs Interrupted by a READ ..................................................................................................................... 62
Burst WRITE Command .................................................................................................................................. 62
WRITEs Interrupted by a WRITE ................................................................................................................. 65
BURST TERMINATE Command ...................................................................................................................... 65
Write Data Mask ............................................................................................................................................. 67
PRECHARGE Command ................................................................................................................................. 68
READ Burst Followed by PRECHARGE ......................................................................................................... 69
WRITE Burst Followed by PRECHARGE ....................................................................................................... 70
Auto Precharge ........................................................................................................................................... 71
READ Burst with Auto Precharge ................................................................................................................. 71
WRITE Burst with Auto Precharge ............................................................................................................... 72
REFRESH Command ...................................................................................................................................... 74
REFRESH Requirements ............................................................................................................................. 80
SELF REFRESH Operation ............................................................................................................................... 82
Partial-Array Self Refresh – Bank Masking .................................................................................................... 83
Partial-Array Self Refresh – Segment Masking .............................................................................................. 84
MODE REGISTER READ ................................................................................................................................. 85
Temperature Sensor ................................................................................................................................... 87
DQ Calibration ........................................................................................................................................... 89
MODE REGISTER WRITE Command ............................................................................................................... 91
MRW RESET Command .............................................................................................................................. 91
MRW ZQ Calibration Commands ................................................................................................................ 92
ZQ External Resistor Value, Tolerance, and Capacitive Loading ..................................................................... 94
Power-Down .................................................................................................................................................. 94
Deep Power-Down ........................................................................................................................................ 101
Input Clock Frequency Changes and Stop Events ............................................................................................ 102
Input Clock Frequency Changes and Clock Stop with CKE LOW .................................................................. 102
Input Clock Frequency Changes and Clock Stop with CKE HIGH ................................................................. 103
NO OPERATION Command ........................................................................................................................... 103
Simplified Bus Interface State Diagram ....................................................................................................... 103
Truth Tables .................................................................................................................................................. 105
Electrical Specifications ................................................................................................................................. 113
Absolute Maximum Ratings ....................................................................................................................... 113
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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