参数资料
型号: MT45W2MV16BAFB-601WT
元件分类: SRAM
英文描述: 2M X 16 PSEUDO STATIC RAM, 60 ns, PBGA54
封装: FBGA-54
文件页数: 20/55页
文件大小: 816K
代理商: MT45W2MV16BAFB-601WT
2 MEG x 16
ASYNC/PAGE/BURST CellularRAM MEMORY
ADVANCE
09005aef80ec6f63
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Burst CellularRAM_32.fm - Rev. A 2/18/04 EN
27
2004 Micron Technology, Inc. All Rights Reserved.
NOTE:
1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).
2. Low-Z to High-Z timings are tested with the circuit shown in Figure 21 on page 25. The High-Z timings measure a
100mV transition from either VOH or VOL toward VCCQ/2.
3. High-Z to Low-Z timings are tested with the circuit shown in Figure 21 on page 25. The Low-Z timings measure a
100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL.
4. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.
Table 17:
Burst READ Cycle Timing Requirements1
PARAMETER
SYMBOL
-701
-706, -856
UNITS
NOTES
MIN
MAX
MIN
MAX
Burst to READ Access Time
tABA
35
55
ns
CLK to Output Delay
tACLK
6.5
10
ns
Burst OE# LOW to Output Delay
tBOE
20
ns
CE# HIGH between Subsequent Mixed-Mode Operations tCBPH
5
ns
CE# LOW to WAIT Valid
tCEW
17.5
1
7.5
ns
CLK Period
tCLK
9.62
20
15
20
ns
4
CE# Setup Time to Active CLK Edge
tCSP
4
20
5
20
ns
Hold Time from Active CLK Edge
tHD
22
ns
Chip Disable to DQ and WAIT High-Z Output
tHZ
8
ns
2
CLK Rise or Fall Time
tKHKL
1.6
ns
CLK to WAIT Valid
tKHTL
6.5
10
ns
CLK to DQ High-Z Output
tKHZ
38
ns
CLK to Low-Z Output
tKLZ
25
ns
Output HOLD from CLK
tKOH
2
ns
CLK HIGH or LOW Time
tKP
3
ns
Output Disable to DQ High-Z Output
tOHZ
8
ns
2
Output Enable to Low-Z Output
tOLZ
5
ns
3
Setup Time to Active CLK Edge
tSP
3
ns
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