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| 型号： | MXB7846EUE+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 19/24页 |
| 文件大小： | 0K |
| 描述： | IC CNTRLR TOUCH RES 16TSSOP |
| 其它有关文件： | Automotive Product Guide |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 温度传感器 |
| 输入类型： | 模拟 |
| 输出类型： | 数字 |
| 接口： | 4 线 |
| 电流 - 电源： | 950µA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 带卷 (TR) |
MXB7846
2.375V to 5.25V, 4-Wire Touch-Screen Controller
with Internal Reference and Temperature Sensor
4
_______________________________________________________________________________________
Note 1: Tested at VDD = 2.7V.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: Offset nulled.
Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5: Resistance measured from the source to drain of the switch.
Note 6: External load should not change during conversion for specified accuracy.
Note 7: ADC performance is limited by the conversion noise floor, typically 300VP-P. An external reference below 2.5V can com-
promise the ADC performance.
Note 8: Difference between Temp0 and Temp1. No calibration necessary.
TIMING CHARACTERISTICS (Figure 1)
(VDD = 2.7V to 3.6V, VREF = 2.5V, fDCLK = 2MHz (50% duty cycle), fSAMPLE = 125kHz, 12-bit mode, 0.1F capacitor at REF, TA =
TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS (Figure 1)
Acquisition Time
tACQ
1.5
s
DCLK Clock Period
tCP
500
ns
DCLK Pulse Width High
tCH
200
ns
DCLK Pulse Width Low
tCL
200
ns
DIN-to-DCLK Setup Time
tDS
100
ns
DIN-to-DCLK Hold Time
tDH
0ns
CS Fall-to-DCLK Rise Setup Time
tCSS
100
ns
CS Rise-to-DCLK Rise Ignore
tCSH
0ns
DCLK Falling-to-DOUT Valid
tDO
CLOAD = 50pF
200
ns
CS Rise-to-DOUT Disable
tTR
CLOAD = 50pF
200
ns
CS Fall-to-DOUT Enable
tDV
CLOAD = 50pF
200
ns
DCLK Falling-to-BUSY Rising
tBD
200
ns
CS Falling-to-BUSY Enable
tBDV
200
ns
CS Rise-to-BUSY Disable
tBTR
200
ns
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