参数资料
型号: N74F374N
厂商: NXP Semiconductors N.V.
元件分类: 通用总线功能
英文描述: Octal transparent latch (3-State); Octal D flip-flop (3-State)
封装: N74F373D<SOT163-1 (SO20)|<<http://www.nxp.com/packages/SOT163-1.html<1<week 4, 2004,;N74F373D<SOT163-1 (SO20)|<<http://www.nxp.com/packages/SOT163-1.html<1<week 4,
文件页数: 2/13页
文件大小: 119K
代理商: N74F374N
Philips Semiconductors
Product data
74F373/74F374
Latch/flip-flop
74F373 Octal transparent latch (3-State)
74F374 Octal D-type flip-flop (3-State)
2
2002 Nov 20
FEATURES
8-bit transparent latch — 74F373
8-bit positive edge triggered register — 74F374
3-State outputs glitch free during power-up and power-down
Common 3-State output register
Independent register and 3-State buffer operation
SSOP Type II Package
DESCRIPTION
The 74F373 is an octal transparent latch coupled to eight 3-State
output devices. The two sections of the device are controlled
independently by enable (E) and output enable (OE) control gates.
The data on the D inputs is transferred to the latch outputs when the
enable (E) input is HIGH. The latch remains transparent to the data
input while E is HIGH, and stores the data that is present one set-up
time before the HIGH-to-LOW enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active-LOW output enable (OE) controls all eight 3-State buffers
independent of the latch operation. When OE is LOW, latched or
transparent data appears at the output.
When OE is HIGH, the outputs are in high impedance “off” state,
which means they will neither drive nor load the bus.
The 74F374 is an 8-bit edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by clock (CP) and output enable (OE) control gates.
The register is fully edge triggered. The state of the D input, one
set-up time before the LOW-to-HIGH clock transition is transferred
to the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active-LOW output enable (OE) controls all eight 3-State buffers
independent of the register operation. When OE is LOW, the data in
the register appears at the outputs. When OE is HIGH, the outputs
are in high impedance “off” state, which means they will neither drive
nor load the bus.
TYPE
TYPICAL
PROPAGATION
DELAY
TYPICAL SUPPLY
CURRENT
(TOTAL)
74F373
4.5 ns
35 mA
TYPE
TYPICAL f
max
TYPICAL SUPPLY
CURRENT
(TOTAL)
74F374
165 MHz
55 mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5 V
±
10%, T
amb
= 0
°
C to +70
°
C
PKG DWG #
20-pin plastic DIP
N74F373N, N74F374N
SOT146-1
20-pin plastic SOL
N74F373D, N74F374D
SOT163-1
20-pin plastic SSOP type II
N74F373DB, N74F374DB
SOT339-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH / LOW
LOAD VALUE
HIGH/LOW
20
μ
A
/
0.6 mA
20
μ
A
/
0.6 mA
20
μ
A
/
0.6 mA
20
μ
A
/
0.6 mA
D0 - D7
Data inputs
1.0 / 1.0
E (74F373)
Enable input (active-HIGH)
1.0 / 1.0
OE
Output enable inputs (active-LOW)
1.0 / 1.0
CP (74F374)
Clock pulse input (active rising edge)
1.0 / 1.0
Q0 - Q7
3-State outputs
150 / 40
3.0 mA / 24 mA
NOTE:
One (1.0) FAST unit load is defined as: 20
μ
A in the HIGH state and 0.6 mA in the LOW state.
相关PDF资料
PDF描述
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相关代理商/技术参数
参数描述
N74F374N,602 功能描述:触发器 OCTAL D-F/F 3-STATE RoHS:否 制造商:Texas Instruments 电路数量:2 逻辑系列:SN74 逻辑类型:D-Type Flip-Flop 极性:Inverting, Non-Inverting 输入类型:CMOS 输出类型: 传播延迟时间:4.4 ns 高电平输出电流:- 16 mA 低电平输出电流:16 mA 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:X2SON-8 封装:Reel
N74F374NA 制造商:North American Philips Discrete Products Div 功能描述:74F374NA
N74F377AD 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Octal D-type flip-flop with enable
N74F377ADB 制造商:未知厂家 制造商全称:未知厂家 功能描述:Octal D-Type Flip-Flop
N74F377AD-T 制造商:未知厂家 制造商全称:未知厂家 功能描述:Octal D-Type Flip-Flop