Philips Semiconductors
Product data
74F373/74F374
Latch/flip-flop
2002 Nov 20
6
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
LIMITS
UNIT
CONDITIONS
1
MIN
TYP
2
MAX
V
OH
HIGH level output voltage
HIGH-level output voltage
V
= MIN, V
= MAX,
CC
V
IH
= MIN, I
OH
= MAX
±
10%V
CC
±
5%V
CC
±
10%V
CC
±
5%V
CC
2.4
V
IL
,
2.7
3.4
V
V
OL
LOW level output voltage
LOW-level output voltage
V
= MIN, V
= MAX,
CC
V
IH
= MIN, I
OL
= MAX
0.35
0.50
V
IL
,
0.35
0.50
V
V
IK
I
I
I
IH
I
IL
I
OZH
I
OZL
I
OS
I
CC
Input clamp voltage
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0 V
V
CC
= MAX, V
I
= 2.7 V
V
CC
= MAX, V
I
= 0.5 V
V
CC
= MAX, V
O
= 2.7 V
V
CC
= MAX, V
O
= 0.5 V
V
CC
= MAX
V
CC
= MAX
–0.73
–1.2
V
Input current at maximum input voltage
100
μ
A
μ
A
High-level input current
20
Low-level input current
–0.6
mA
Off-state output current, high-level voltage applied
50
μ
A
μ
A
Off-state output current, low-level voltage applied
Short-circuit output current
3
–50
–60
–150
mA
Supply current (total)
74F373
35
60
mA
74F374
57
86
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
= 5 V, T
= 25
°
C.
3. Not more than one output should be shorted at a time. For testing I
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
amb
= +25
°
C
V
CC
= +5.0 V
C
L
= 50 pF; R
L
= 500
MIN
TYP
T
amb
= 0
°
C to +70
°
C
V
CC
= +5.0 V
±
10%
C
L
= 50 pF; R
L
= 500
MIN
SYMBOL
PARAMETER
TEST
UNIT
CONDITION
MAX
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation delay
Dn to Qn
Waveform 3
3.0
2.0
5.3
3.7
7.0
5.0
3.0
2.0
8.0
6.0
ns
Propagation delay
E to Qn
74F373
Waveform 2
5.0
3.0
9.0
4.0
11.5
7.0
5.0
3.0
12.0
8.0
ns
Output enable time
to HIGH or LOW level
Waveform 6
Waveform 7
2.0
2.0
5.0
5.6
11.0
7.5
2.0
2.0
11.5
8.5
ns
Output disable time
from HIGH or LOW level
Waveform 6
Waveform 7
2.0
2.0
4.5
3.8
6.5
5.0
2.0
2.0
7.0
6.0
ns
f
max
Maximum clock frequency
Waveform 1
150
165
140
ns
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation delay
CP to Qn
74F374
Waveform 1
3.5
3.5
5.0
5.0
7.5
7.5
3.0
3.0
8.5
8.5
ns
Output enable time
to HIGH or LOW level
Waveform 6
Waveform 7
2.0
2.0
9.0
5.3
11.0
7.5
2.0
2.0
12.0
8.5
ns
Output disable time
from HIGH or LOW level
Waveform 6
Waveform 7
2.0
2.0
5.3
4.3
6.0
5.5
2.0
2.0
7.0
6.5
ns