参数资料
型号: NB3N49152MNTXG
厂商: ON Semiconductor
文件页数: 1/6页
文件大小: 0K
描述: IC CLK GEN VCXO LVPECL 20QFN
标准包装: 3,000
系列: PureEdge™
类型: *
PLL:
输入: 晶体
输出: LVPECL
电路数: 1
比率 - 输入:输出: 1:1
差分 - 输入:输出: 无/是
频率 - 最大: 491.52MHz
除法器/乘法器: 无/是
电源电压: 2.97 V ~ 3.63 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-VFQFN 裸露焊盘
供应商设备封装: 20-QFN(4x4)
包装: 带卷 (TR)
Semiconductor Components Industries, LLC, 2012
April, 2012 Rev. 0
1
Publication Order Number:
NB3N15552MN/D
NB3Nxxxxx - VCXO Series
3.3V PureEdge
] VCXO
Clock Generator with
Differential LVPECL Outputs
Description
The NB3NXXXXX series voltagecontrolled crystal oscillator
(VCXO) devices are designed to meet today’s requirements for 3.3 V
LVPECL clock generation applications. These devices use an external
high Q fundamental mode pullable crystal and Phase Locked Loop
(PLL) multiplier to provide a wide range of frequencies from 60 MHz
to 700 MHz (factory configurable per user specifications) with a
pullable range of
±100 ppm. The siliconbased PureEdge products
provides users with exceptional frequency stability and reliability.
They produce an ultra low jitter and phase noise LVPECL differential
out put . The NB3NXXXXX series are members of
ON Semiconductor’s PureEdge clock family that provides accurate
and precision clock generation solutions.
Available in the industry standard 4 mm x 4 mm QFN20 package.
Features
LVPECL Differential Output
Operating Range: 3.3 V ±10%
Ultra Low Jitter and Phase Noise 0.5 ps (12 kHz 20 MHz)
245 ps Typical Rise and Fall Times
Factory Configurable Frequencies from 60 MHz to 700 MHz (see
Standard Frequencies in the Ordering Information Table in page 5)
Pullable Range Minimum of ±100 ppm
Control Voltage with Positive Slope
40°C to +85°C Ambient Operating Temperature
These Devices are PbFree and are RoHS Compliant
Applications
Networking
SONET
10 Gigabit Ethernet
Networking Base Stations
Broadcasting
MARKING
DIAGRAM
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the
package dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
(*Note: Microdot may be in either location)
QFN20
MN SUFFIX
CASE 485E
XXXXX = Frequency XXX.XX
A
= Assembly Location
L, WL
= Wafer Lot
Y
= Year
W, WW = Work Week
G or G = PbFree Package
NB3N
xxxxx
ALYWG
G
1
20
Figure 1. Simplified Block Diagram of
NB3Nxxxxx
VDD
CLK
GND
OE
VC
XIN
XOUT
PLL
Clock
Multiplier
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