参数资料
| 型号： | NB3N65027DTR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 6/7页 |
| 文件大小： | 0K |
| 描述： | IC CLK SYNTHESIZER 3PLL 20QSOP |
| 标准包装： | 1 |
| 类型： | * |
| PLL： | 是 |
| 输入： | LVCMOS，LVTTL，晶体 |
| 输出： | LVCMOS，LVTTL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:7 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 125MHz |
| 除法器/乘法器： | 是/是 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 20-QSOP |
| 包装： | 标准包装 |
| 其它名称： | NB3N65027DTR2GOSDKR |
NB3N65027
http://onsemi.com
6
External Components
The NB3N65027 requires a minimum number of external
components for proper operation.
Decoupling Capacitor
Decoupling capacitors of 0.01
mF must be connected
between each VDD and GND (pins 4 and 6, pins 16 and 14),
as close to the device as possible. For optimum device
performance, the decoupling capacitor should be mounted
on the component side of the PCB. Avoid the use of vias in
the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50
W trace (a commonly used trace
impedance), place a 33
W resistor in series with the clock
line as close to the clock output pin as possible. The nominal
impedance of the clock output is 20
W.
Crystal Information
The crystal used should be a fundamental mode (do not
use third overtone), parallel resonant. Crystal load
capacitors should be connected from pins X1 to ground and
X2 to ground to optimize the frequency accuracy, See
Figure 1.
A crystal in parallel resonance will require the spec CL as
a balanced loading for each side of the crystal, so CL is
distributed in two equal series load caps, CL1 and CL2. All
stray and additional capacitance must be subtracted from
this total loading.
1. Crystal load capacitance, CL, is:
CL +
CL1 @ CL2
CL1 ) CL2
Where:
CL = Crystal Spec Load Capacitance
CL1 = X1 Pin Total Load Capacitance
CL2 = X2 Pin Total Load Capacitance
2. If CL = 18 pF, then CL1 = CL2 = 2CL, or 36 pF.
Stray capacitance, CLS1 and CLS2, must be considered and
subtracted from each total load capacitance, CL1 and CL2.
Furthermore:
CL1 = CLX1 + CLS1
CL2 = CLX2 + CLS2
Where:
CLX1 = Load Capacitor Board Component for CL1
CLX2 = Load Capacitor Board Component for CL2
CLS1 = Stray Load Capacitance at X1
CLS2 = Stray Load Capacitance at X2
As an example, for 4 pF of stray capacitance, CLS1 = CLS2
= 4 pF, then, Board Component Capacitors CLX1 = CLX2 =
2CL – CLS(1or2), or 36 pF – 4 pF = 32 pF.
Table 14. RECOMMENDED CRYSTAL PARAMETERS
Parameter
Value
Crystal Cut
Fundamental AT Cut
Resonance
Parallel Resonance
Load Capacitance
18 pF
Operating Range
40 to +85°C
Shunt Capacitance
5 pF Max
Equivalent Series Resistance (ESR)
50 W Max
Correlation Drive Level
1.0 mW Max
ORDERING INFORMATION
Device
Package
Shipping
NB3N65027DTG
QSOP20
(PbFree)
55 Units / Rail
NB3N65027DTR2G
QSOP20
(PbFree)
2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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