参数资料
| 型号： | NB4L6254MNR4G |
| 厂商： | ON Semiconductor |
| 文件页数： | 5/11页 |
| 文件大小： | 0K |
| 描述： | IC CLK BUFFER MUX 1:6/1:3 32-QFN |
| 标准包装： | 1,000 |
| 类型： | 扇出缓冲器（分配），多路复用器 |
| 电路数： | 1 或 2 |
| 比率 - 输入:输出： | 1:6，1:3 |
| 差分 - 输入:输出： | 是/是 |
| 输入： | LVCMOS，LVPECL |
| 输出： | LVPECL |
| 频率 - 最大： | 3GHz |
| 电源电压： | 2.375 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 带卷 (TR) |
NB4L6254
http://onsemi.com
3
Table 1. PIN DESCRIPTION
Pin Name
I/O
Description
CLK0, CLK0
LVPECL Input
Differential reference clock signal input 0.
CLK1, CLK1
LVPECL Input
Differential reference clock signal input 1.
OEAb, OEB
LVCMOS Input
Output Enable
SEL0, SEL1
LVCMOS Input
Clock Switch Select
QA[02], QA[02]
QB[02], QB[02]
LVPECL Output
Differential LVPECL Clock Outputs, (banks A and B) Typically terminated with 50 W
resistor to VCC – 2.0 V.
GND
Power Supply
Negative Supply Voltage
VCC
Power Supply
Positive supply voltage. All VCC pins must be connected to the positive power supply
for correct DC and AC operation.
EP
The exposed pad (EP) on the QFN32 package bottom is thermally connected to the
die for improved heat transfer out of the package. THe exposed pad must be attached
to a heatsinking conduit. The pad is electrically connected to GND.
Table 2. FUNCTION TABLE
Control
Default
0
1
OEA
0
QA[02], QA[02] are active. Deassertion of
OEA can be asynchronous to the reference
clock without generation of output runt pulses
QA[02] = L, QA[02] = H (outputs disabled). Assertion of
OE can be asynchronous to the reference clock without
generation of output runt pulses
OEB
0
QB[02], QB[02] are active. Deassertion of
OEB can be asynchronous to the reference
clock without generation of output runt pulses
QB[02] = L, QB[02] = H (outputs disabled). Assertion of
OE can be asynchronous to the reference clock without
generation of output runt pulses
SEL0,
SEL1
00
Refer to Table 3
Table 3. CLOCK SELECT CONTROL
SEL0
SEL1
CLK0 Routed To
CLK1 Routed to
Application Mode
0
QA[0:2] and QB[0:2]
1:6 Fanout of CLK0
0
1
QA[0:2] and QB[0:2]
1:6 Fanout of CLK1
1
0
QA[0:2]
QB[0:2]
Dual 1:3 Buffer
1
QB[0:2]
QA[0:2]
Dual 1:3 Buffer (Crossed)
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