参数资料
| 型号： | NB4L7210MNG |
| 厂商： | ON Semiconductor |
| 文件页数： | 4/11页 |
| 文件大小： | 0K |
| 描述： | IC CLK BUFF MUX 2:10 2GHZ 52-QFN |
| 标准包装： | 260 |
| 类型： | 扇出缓冲器（分配），多路复用器 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:10 |
| 差分 - 输入:输出： | 是/是 |
| 输入： | CML，LVCMOS，LVDS，LVPECL，LVTTL |
| 输出： | LVPECL |
| 频率 - 最大： | 2GHz |
| 电源电压： | 2.375 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 52-VFQFN 裸露焊盘 |
| 供应商设备封装： | 52-QFN（8x8） |
| 包装： | 托盘 |
NB4L7210
http://onsemi.com
2
Figure 2. Pin Configuration (Top View)
VCC3
Q3
VCC4
GND
SLOAD
VTCLK0
CLK0
14 15 16 17
52 51 50 49
39
38
37
36
1
2
3
4
NB4L7210
Exposed Pad (EP)
Q4
GND
Q5
CLK0
VTCLK0
GND
VTCLK1
35
34
33
32
5
6
7
8
Q5
VCC5
Q6
CLK1
VTCLK1
SDATA
31
30
29
28
9
10
11
12
VCC6
GND
27
13
18 19 20 21
48 47 46 45
22 23 24 25
44 43 42 41
26
40
SDA
TAOUT
VCC
VCC0
Q0
SCLK
VCC
VCC9
Q9
Q0
VCC1
Q1
Q9
VCC8
Q8
VCC2
Q2
GND
VCC7
Q7
GND
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1, 7, 13, 25, 26, 33,
40, 41
GND
Supply
Negative Supply pins must be all externally connected to a power
supply to guarantee proper operation.
2
SLOAD
LVCMOS, LVTTL
Serial Load and Latch control input pin. Defaults LOW when float-
ing open
.
3, 6, 8, 11
VTCLK0, VTCLK0,
VTCLK1, VTCLK1
Termination
Internal 50 Ohms Termination Resistor connection Pins. In the
differential configuration when the input termination pins are con-
nected to the common termination voltage.
4, 9
CLK0, CLK1
Differential LVPECL,
CML, or LVDS
CLOCK Input (TRUE). If no signal is applied then the device may
be susceptible to self oscillation.
5, 10
CLK0, CLK1
Differential LVPECL,
CML, or LVDS
CLOCK Input (INVERT). If no signal is applied then the device
may be susceptible to self oscillation.
12
SDATA
LVCMOS, LVTTL
Serial Data input pin (for BITS 0:9, a “0” selects CLK1, “1” selects
CLK 0). Defaults LOW when floating open.
14
SCLK
LVCMOS, LVTTL
Serial Load Clock input pin. Defaults LOW when floating open.
15, 16, 19, 22, 27,
30, 36, 39, 44, 47,
50, 51
VCC, VCC9, VCC8,
VCC7, VCC6, VCC5,
VCC4, VCC3, VCC2,
VCC1, VCC0
Supply
Positive Supply pins must be all externally connected to a power
supply to guarantee proper operation.
17, 20, 23, 28, 31,
34, 37, 42, 45, 48
Q[90]
LVPECL
Output (INVERT)
18, 21, 24, 29, 32,
35, 38, 43, 46, 49
Q[90]
LVPECL
Output (TRUE)
52
SDATAOUT
LVCMOS, LVTTL
Serial Data output pin for cascade
Exposed Pad
EP
GND
Exposed Pad. The thermally exposed pad (EP) on package bot-
tom (see case drawing) must be attached to a sufficient heat
sinking conduit for proper thermal operation and must be connec-
ted to GND.
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