参数资料
| 型号： | NB6L11DTR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 11/13页 |
| 文件大小： | 0K |
| 描述： | IC CLK BUFFER TRANSLA 1:2 8TSSOP |
| 产品变化通告： | Product Discontinuation 20/Aug/2008 |
| 标准包装： | 2,500 |
| 类型： | 扇出缓冲器（分配），变换器 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 是/是 |
| 输入： | CML，LVCMOS，LVDS，LVNECL，LVPECL，LVTTL |
| 输出： | ECL |
| 频率 - 最大： | 6GHz |
| 电源电压： | 2.375 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 带卷 (TR) |
NB6L11
http://onsemi.com
7
Table 7. AC CHARACTERISTICS VCC = 0 V; VEE = 3.465 V to 2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V (Note 23)
Symbol
Characteristic
40°C
25°C
85°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
VOUTPP Output Voltage Amplitude
fin v 3 GHz
fin v 6 GHz
480
270
700
300
480
270
700
300
480
270
700
300
mV
fDATA
Maximum Operating Data Rate
6
Gb/s
tPLH,
tPHL
Propagation Delay to
Output Differential @ 1 GHz
D to Q, Q
110
150
190
110
150
200
120
160
220
ps
tSKEW
Duty Cycle Skew
Within Device Skew
(Note 24)
DevicetoDevice Skew
2
5
15
10
15
60
2
5
15
10
15
60
2
5
15
10
15
60
ps
tJITTER
RMS Random Clock Jitter
(Note 25)
fin v 6 GHz
PeaktoPeak Data Dependent Jitter
(Note 26)
fin v 6 Gb/s
0.2
2
1
12
0.2
2
1
12
0.2
2
1
12
ps
VINPP
Input Voltage Swing / Sensitivity
(Differential Configuration) (Note 27)
75
700
2500
75
700
2500
75
700
2500
mV
tr
tf
Output Rise/Fall Times @ 1 GHz
Q, Q
(20% 80%)
30
75
120
30
75
120
30
75
120
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
23.Measured using a 800 mV source, 50% duty cycle clock source. All loading with 50 W to VCC 2.0 V. Input edge rates 40 ps (20% 80%).
24.See Figure 13 tskew = |tPLH tPHL| for a nominal 50% differential clock input waveform. Skew is measured between outputs under identical
transitions and conditions @ 1 GHz.
25.Additive RMS jitter with 50% duty cycle clock signal at 6 GHz.
26.Additive PeaktoPeak data dependent jitter with NRZ PRBS 2231 data rate at 6 Gb/s.
27.VINPP(max) cannot exceed VCC VEE (applicable only when VCC VEE < 2500 mV). Input voltage swing is a singleended measurement
operating in differential mode
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
12
4
5
6
7
8
3
OUTPUT
VOL
TAGE
AMPLITUDE
(V)
Figure 2. Output Voltage Amplitude (VOUTPP)
versus Input Clock Frequency (fIN) and
Temperature at VCC VEE = 3.3 V
INPUT CLOCK FREQUENCY (GHz)
85°C
40°C
25°C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
1
2
34
5
6
78
OUTPUT
VOL
TAGE
AMPLITUDE
(V)
40°C
85°C
25°C
Figure 3. Output Voltage Amplitude (VOUTPP)
versus Input Clock Frequency (fIN) and
Temperature at VCC VEE = 2.5 V
INPUT CLOCK FREQUENCY (GHz)
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