参数资料
型号: NB6L295MMNG
厂商: ON Semiconductor
文件页数: 10/13页
文件大小: 0K
描述: IC DELAY LINE 511TAP 24-QFN
标准包装: 92
标片/步级数: 512
功能: 多重,可编程
延迟到第一抽头: 3.2ns,6.2ns
接头增量: 11ps
可用的总延迟: 3.2ns ~ 8.5ns,6.2ns ~ 16.6ns
独立延迟数: 2
电源电压: 2.375 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-VFQFN 裸露焊盘
供应商设备封装: 24-QFN(4x4)
包装: 管件
其它名称: NB6L295MMNG-ND
NB6L295MMNGOS
NB6L295M
http://onsemi.com
6
Table 5. AC CHARACTERISTICS VCC = VCC0 = VCC1 = 2.375 V to 3.6 V, GND = 0 V, TA = 40°C to +85°C (Note 10)
Symbol
Characteristic
Min
Typ
Max
Unit
fSCLK
Serial Clock Input Frequency, 50% Duty Cycle
20
MHz
VOUTPP Output Voltage Amplitude (@ VINPPmin) fin ≤ 1.5 GHz
(Note 15) (See Figure 23)
210
380
mV
fDATA
Maximum Data Rate (Note 14)
2.5
Gb/s
tRange
Programmable Delay Range (@ 50 MHz)
Dual Mode IN0/IN0 to Q0/Q0 or IN1/IN1 to Q1/Q1
Extended Mode
IN0/IN0 to Q1/Q1
0
5.7
11.2
6.9
13.7
ns
tSKEW
Duty Cycle Skew (Note 11)
Within Device Skew Dual Mode
D[8:0] = 0
D[8:0] = 1
0
1
55
67
4
96
170
ps
Lin
Linearity (Note 12)
$15
$20
ps
ts
Setup Time (@ 20 MHz)
SDIN to SCLK
SCLK to SLOAD
EN to SDIN
0.5
1.5
0.5
0.3
1.0
ns
th
Hold Time
SDIN to SCLK
SCLK to SLOAD
EN to SLOAD
1.0
0.5
0.6
ns
tpwmin
Minimum Pulse Width SLOAD
1
ns
tJITTER
Random Clock Jitter RMS; SETMIN to SETMAX
(Note 13)
fin ≤ 1.5 GHz
Dual Mode IN0/IN0 to Q0/Q0 or IN1/IN1 to Q1/Q1
Extended Mode
IN0/IN0 to Q1/Q1
Deterministic Jitter; SETMIN to SETMAX (Note 14) fD
ATA v 2.5 Gbps
Dual Mode IN0/IN0 to Q0/Q0 or IN1/IN1 to Q1/Q1
2
4
2
6
12
15
ps
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 15)
150
VCC GND
mV
tr, tf
Output Rise/Fall Times (@ 50 MHz), (20% 80%)
Qx, Qx
85
100
150
ps
Symbol
Characteristic
405C
+255C
+855C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
tPLH,
tPHL
Propagation Delay (@ 50 MHz)
Dual Mode IN0/IN0 to Q0/Q0 or IN1/IN1 to Q1/Q1
D[8:0] = 0
D[8:0] = 1
Extended Mode
IN0/IN0 to Q1/Q1
D[8:0] = 0
D[8:0] = 1
2.7
7.2
5.0
14
3.1
8.5
5.9
16.4
3.3
9.1
6.5
17.7
2.8
7.4
5.2
14.4
3.2
8.5
6.2
16.6
3.5
9.6
6.6
18.7
3.1
8.6
5.9
17
3.4
9.3
6.6
19
3.8
10.7
7.3
21
ns
Dt
Step Delay
(Selected D Bit HIGH All Others LOW)
D0 HIGH
D1 HIGH
D2 HIGH
D3 HIGH
D4 HIGH
D5 HIGH
D6 HIGH
D7 HIGH
D8 HIGH
8.4
16.4
41.2
85
178
360
722
1448
2903
12.4
25.1
58.3
108
210
405
796
1579
3143
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10.Measured by forcing VINPPmin and VINPPmax from a 50% duty cycle clock source, VCMR (min and max). All loading with an external
RL = 50 W to VCC. See Figure 20. Input edge rates 40 ps (20% 80%).
11. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw and Tpw+ @ 0.5 GHz.
12.Deviation from a linear delay (actual Min to Max) in the Dual Mode 511 programmable steps; 3.3 V @ 25°C, 400 mV VINPP.
13.Additive Random CLOCK jitter with 50% duty cycle input clock signal. 1000 WFMS, JIT3 Software.
14.NRZ data at PRBS23 and K28.5. 10,000 WFMS, TDS8000.
15.Input and output voltage swing is a singleended measurement operating in differential mode.
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