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参数资料
| 型号： | NB6L295MMNGEVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 11/13页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL NB6L295MMN CLK DELAY |
| 标准包装： | 1 |
| 主要目的： | 计时，时钟分配 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | NB6L295M |
| 次要属性： | SMA 连接器 |
| 已供物品： | 板 |
| 其它名称： | NB6L295MMNGEVB-ND NB6L295MMNGEVBOS |
NB6L295M
http://onsemi.com
7
Serial Data Interface Programming
The NB6L295M is programmed by loading the 11Bit SHIFT REGISTER using the SCLK, SDATA and SLOAD inputs.
The 11 SDATA bits are 1 PSEL bit, 1 MSEL bit and 9 delay value data bitsD[8:0]. A separate 11bit load cycle is required to
program the delay data value of each channel, PD0 and PD1. For example, at powerup two load cycles will be needed to initially
set PD0 and PD1; Dual Mode Operation as shown in Figures 3 and 4 and Extended Mode Operation as shown in Figures 5
and 6.
DUAL MODE OPERATIONS
PD0 Programmable Delay
Control
Bits
Value
PD1 Programmable Delay
Control
Bits
Value
0/1
0
0/1
0
1
D8
D7
D6
D5
D4
D3
D2
D1
D0
MSEL PSEL Bit
Name
D8
D7
D6
D5
D4
D3
D2
D1
D0
MSEL PSEL Bit
Name
(MSB)
(LSB)
Name
(MSB)
(LSB)
Name
Figure 3. PDO Shift Register
Figure 4. PD1 Shift Register
EXTENDED MODE OPERATIONS
PD0 Programmable Delay
Control
Bits
Value
PD1 Programmable Delay
Control
Bits
Value
0/1
1
0
0/1
1
D8
D7
D6
D5
D4
D3
D2
D1
D0
MSEL PSEL Bit
Name
D8
D7
D6
D5
D4
D3
D2
D1
D0
MSEL PSEL Bit
Name
(MSB)
(LSB)
Name
(MSB)
(LSB)
Name
Figure 5. PDO Shift Register
Figure 6. PD1 Shift Register
Refer to Table 6, Channel and Mode Select BIT Functions. In a load cycle, the 11Bit Shift Register least significant bit
(clocked in first) is PSEL and will determine which channel delay buffer, either PDO (LOW) or PD1 (HIGH), will latch the
delay data value D[8:0]. The MSEL BIT determines the Delay Mode. When set LOW, the Dual Delay Mode is selected and
the device uses both channels independently. A pulse edge entering IN0/IN0 is delayed according to the values in PD0 and exits
from Q0/Q0. An input signal pulse edge entering IN1/IN1 is delayed according to the values in PD1 and exits from Q1/Q1.
When MSEL is set HIGH, the Extended Delay Mode is selected and an input signal pulse edge enters IN0 and IN0 and flows
through PD0 and is extended through PD1 to exit at Q1 and Q1. The most significant 9bits, D[8:0] are delay value data for
both channels. See Figure 7.
Table 6. CHANNEL AND MODE SELECT BIT FUNCTIONS
BIT Name
Function
PSEL
0 Loads Data to PD0
1 Loads Data to PD1
MSEL
0 Selects Dual Programmable Delay Paths, 3.1 ns to 8.8 ns Delay Range for Each Path
1 Selects Extended Delay Path from IN0/IN0 to Q1/Q1, 6.0 ns to 17.2 ns Delay Range; Disables Q0/Q0 Outputs,
Q0LOW, Q0HIGH.
D[8:0]
Select one of 512 Delay Values
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相关代理商/技术参数 |
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|---|---|
| NB6L295MMNTXG | 功能描述:延迟线/计时元素 CML DUAL PROG DELAY RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 传播延迟时间:1000 ps 工作温度范围: 封装 / 箱体:QFN-24 封装:Tube |
| NB6L295MNG | 功能描述:延迟线/计时元素 LVPECL DUAL PRG DLAY RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 传播延迟时间:1000 ps 工作温度范围: 封装 / 箱体:QFN-24 封装:Tube |
| NB6L295MNGEVB | 功能描述:电源管理IC开发工具 NB6L295 EVAL BOARD RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
| NB6L295MNTXG | 功能描述:延迟线/计时元素 LVPECL DUAL PRG DLAY RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 传播延迟时间:1000 ps 工作温度范围: 封装 / 箱体:QFN-24 封装:Tube |
| NB6L56MNG | 功能描述:时钟缓冲器 TSMC 2.5V/3.3V DUAL DIFF RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
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