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参数资料
| 型号： | NB6L295MMNGEVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 12/13页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL NB6L295MMN CLK DELAY |
| 标准包装： | 1 |
| 主要目的： | 计时，时钟分配 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | NB6L295M |
| 次要属性： | SMA 连接器 |
| 已供物品： | 板 |
| 其它名称： | NB6L295MMNGEVB-ND NB6L295MMNGEVBOS |
NB6L295M
http://onsemi.com
8
D8
D7
D6
D5
D4
D3
D2
D1
D0
MSEL
PSEL
Figure 7. Serial Data Interface, Shift Register, Data Latch, Programmable Delay Channels
Load Cycle Required for Each Channel
D8
D7
D6
D5
D4
D3
D2
D1
D0
D8
D7
D6
D5
D4
D3
D2
D1
D0
01
PD1 Latch
PD0 Latch
PD0 Delay
PD1 Delay
SLOAD
Q1/Q1
Q0/Q0
SDATA
SCLK
11Bit Shift Register
MSEL
Serial Data Interface Loading
Loading the device through the 3 input Serial Data Interface (SDI) is accomplished by sending data into the SDIN pin by
using the SCLK input pin and latching the data with the SLOAD input pin. The 11bit SHIFT REGISTER shifts once per rising
edge of the SCLK input. The serial input SDIN must meet setup and hold timing as specified in the AC Characteristics section
of this document for each bit and clock pulse. The SLOAD line loads the value of the shift register on a LOWtoHIGH edge
transition (transparent state) into a data Latch register and latches the data with a subsequent HIGHtoLOW edge transition.
Further changes in SDIN or SCLK are not recognized by the latched register. The internal multiplexer states are set by the PSEL
and MSEL bits in the SHIFT register. Figure 6 shows the timing diagram of a typical load sequence.
Input EN should be LOW (enabled) prior to SDI programming, then pulled HIGH (disabled) during programming. After
programming, the EN should be returned LOW (enabled) for functional delay operation.
The disabling of EN (HIGH) forces Qx LOW and Qx HIGH and is included during programming to prevent (or mask out)
any potential run pulses or extended pulses which might occur in the internal delay gates programming switching, but it is not
required for programming.
D4
D8
D7
Figure 8. SDI Programming Cycle Timing Diagram (Load Cycle 1 of 2)
SDIN
SCLK
SLOAD
EN
MSB
PSEL MSEL
D0
D1
D2
D3
D5
D6
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
ts SDIN to
SCLK
th SDIN to SCLK
ts SCLK to SLOAD
tH SCLK to SLOAD
EN to SDIN
LSB
EN to SLOAD
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相关代理商/技术参数 |
参数描述 |
|---|---|
| NB6L295MMNTXG | 功能描述:延迟线/计时元素 CML DUAL PROG DELAY RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 传播延迟时间:1000 ps 工作温度范围: 封装 / 箱体:QFN-24 封装:Tube |
| NB6L295MNG | 功能描述:延迟线/计时元素 LVPECL DUAL PRG DLAY RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 传播延迟时间:1000 ps 工作温度范围: 封装 / 箱体:QFN-24 封装:Tube |
| NB6L295MNGEVB | 功能描述:电源管理IC开发工具 NB6L295 EVAL BOARD RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
| NB6L295MNTXG | 功能描述:延迟线/计时元素 LVPECL DUAL PRG DLAY RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 传播延迟时间:1000 ps 工作温度范围: 封装 / 箱体:QFN-24 封装:Tube |
| NB6L56MNG | 功能描述:时钟缓冲器 TSMC 2.5V/3.3V DUAL DIFF RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
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