参数资料
型号: NB7L11MMNR2G
厂商: ON Semiconductor
文件页数: 4/11页
文件大小: 0K
描述: IC CLK/DTA BUF TRNSLA 1:2 16-QFN
标准包装: 3,000
类型: 扇出缓冲器(分配),变换器,数据
电路数: 1
比率 - 输入:输出: 1:2
差分 - 输入:输出: 是/是
输入: CML,LVCMOS,LVDS,LVPECL,LVTTL
输出: CML
频率 - 最大: 8GHz
电源电压: 2.375 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-VFQFN 裸露焊盘
供应商设备封装: 16-QFN(3x3)
包装: 带卷 (TR)
NB7L11M
http://onsemi.com
2
VCC Q1 Q1
VCC
VCC Q0
Q0
VCC
VEE
VTCLK
CLK
VTCLK
56
7
8
16
15
14
13
12
11
10
9
1
2
3
4
NB7L11M
Exposed Pad (EP)
Figure 2. QFN16 Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1
VTCLK
Internal 50 W Termination Pin for CLK
2
CLK
LVPECL, CML,
LVCMOS, LVTTL,
LVDS
Inverted Differential Clock/Data Input. (Note 1)
3
CLK
LVPECL, CML,
LVCMOS, LVTTL,
LVDS
Noninverted Differential Clock/Data Input. (Note 1)
4
VTCLK
Internal 50 W Termination Pin for CLK
5,8,13,16
VCC
Positive Supply Voltage. All VCC pins must be externally connected to a Power Supply
to guarantee proper operation.
6
Q1
CML Output
Inverted CLK output 1 with internal 50 W source termination resistor. (Note 2)
7
Q1
CML Output
Noninverted CLK output 1 with internal 50 W source termination resistor. (Note 2)
9,10,11,12
VEE
Negative Supply Voltage. All VEE pins must be externally connected to a Power Supply
to guarantee proper operation.
14
Q0
CML Output
Inverted CLK output 0 with internal 50 W source termination resistor. (Note 2)
15
Q0
CML Output
Noninverted CLK output 0 with internal 50 W source termination resistor. (Note 2)
EP
Exposed Pad. The thermally exposed pad on package bottom (see case drawing) must
be attached to a heatsinking conduit. It is recommended to connect the EP to the lower
potential (VEE).
1. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage or left open,
and if no signal is applied on CLK and CLK then the device will be susceptible to selfoscillation.
2. CML outputs require 50 W receiver termination resistor to VCC for proper operation.
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