参数资料
| 型号： | NB7L11MMNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 7/11页 |
| 文件大小： | 0K |
| 描述： | IC CLK/DTA BUF TRNSLA 1:2 16-QFN |
| 标准包装： | 3,000 |
| 类型： | 扇出缓冲器（分配），变换器，数据 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 是/是 |
| 输入： | CML，LVCMOS，LVDS，LVPECL，LVTTL |
| 输出： | CML |
| 频率 - 最大： | 8GHz |
| 电源电压： | 2.375 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-VFQFN 裸露焊盘 |
| 供应商设备封装： | 16-QFN（3x3） |
| 包装： | 带卷 (TR) |
NB7L11M
http://onsemi.com
5
Symbol
Characteristic
40°C
25°C
85°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
VOUTPP Output Voltage Amplitude (@VINPPmin)fin ≤ 6 GHz
(See Figure 3)
fin ≤ 8 GHz
280
140
400
300
280
140
400
300
280
140
400
300
mV
fdata
Maximum Operating Data Rate
10
12
10
12
10
12
Gb/s
tPLH,
tPHL
Propagation Delay to Output Differential
70
110
150
70
110
150
70
110
150
ps
tSKEW
Duty Cycle Skew (Note 10)
WithinDevice Skew
DevicetoDevice Skew (Note 11)
2.0
3.0
20
5.0
15
50
2.0
3.0
20
5.0
15
50
2.0
3.0
20
5.0
15
50
ps
tJITTER
RMS Random Clock Jitter (Note 12)
fin = 6 GHz
fin =8 GHz
Peak/Peak Data Dependent Jitter fin = 2.488 Gb/s
(Note 13)
fdata =5 Gb/s
fdata =10 Gb/s
0.2
2.0
3.0
5.0
0.5
5.0
8.0
10
0.2
2.0
3.0
5.0
0.5
5.0
8.0
10
0.2
2.0
3.0
5.0
0.5
5.0
8.0
10
ps
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 14)
75
400
2500
75
400
2500
75
400
2500
mV
tr
tf
Output Rise/Fall Times @ 1 GHz
Q, Q
(20% 80%)
30
60
30
60
30
60
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. Measured by forcing VINPP (TYP) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC.
Input edge rates 40 ps (20% 80%).
10.Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw and Tpw+ @1 GHz.
11. Device to device skew is measured between outputs under identical transition @ 1 GHz.
12.Additive RMS jitter with 50% duty cycle clock signal at 8 GHz & 10 GHz.
13.Additive peaktopeak data dependent jitter with input NRZ data at PRBS 2^231.
14.VINPP (MAX) cannot exceed VCC VEE. Input voltage swing is a singleended measurement operating in differential mode.
Figure 3. Output Voltage Amplitude (VOUTPP) versus
Input Clock Frequency (fin) at Ambient Temperature (Typical)
(VINPP = 400 mV)
INPUT FREQUENCY (GHz)
OUTPUT
VOL
TAGE
AMPLITUDE
(mV)
500
400
300
200
100
0
12
11
10
9
8
7
6
5
4
3
2
1
0
VCC = 3.3 V
VCC = 2.5 V
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