参数资料
型号: NBSG14BAHTBG
厂商: ON Semiconductor
文件页数: 12/13页
文件大小: 0K
描述: IC CLOCK/DATA BUFFER 1:4 16FCBGA
产品变化通告: Product Obsolescence 05/Oct/2010
标准包装: 100
类型: 扇出缓冲器(分配),数据
电路数: 1
比率 - 输入:输出: 1:4
差分 - 输入:输出: 是/是
输入: CML,LVCMOS,LVDS,LVTTL,NECL,PECL,RSECL
输出: RSECL,RSNECL,RSPECL
频率 - 最大: 12GHz
电源电压: 2.375 V ~ 3.465 V
工作温度: -40°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 16-LBGA,FCBGA
供应商设备封装: 16-FCBGA(4x4)
包装: 带卷 (TR)
NBSG14
http://onsemi.com
8
Table 8. AC CHARACTERISTICS for FCBGA16
VCC = 0 V; VEE = 3.465 V to 2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V
Symbol
Characteristic
40°C
25°C
70°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fmax
Maximum Frequency
(See Figure 4) (Note 22)
10.7
12
10.7
12
10.7
12
GHz
tPLH,
tPHL
Propagation Delay to
Output Differential
100
125
150
100
125
150
100
125
150
ps
tSKEW
Duty Cycle Skew (Note 23)
WithinDevice Skew (Note 24)
DevicetoDevice Skew (Note 25)
2
6
25
10
15
50
2
6
25
10
15
50
2
6
25
10
15
50
ps
tJITTER
RMS Random Clock Jitter
(Figure 4) (Note 27)
fin < 10 GHz
PeaktoPeak Data Dependent Jitter
(Note 28)
fin < 10 Gb/s
0.2
10
1
0.2
10
1
0.2
10
1
ps
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 26)
75
2600
75
2600
75
2600
mV
tr
tf
Output Rise/Fall Times
Q, Q
(20% 80%) @ 1 GHz
20
30
55
20
30
55
20
30
55
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
22.Measured using a 500 mV source, 50% duty cycle clock source. All outputs loaded with 50 W to VCC 1.5 V. Input edge rates 40 ps
(20% 80%).
23.See Figure 6. tSKEW = |tPLH tPHL| for a nominal 50% Differential Clock Input Waveform.
24.WithinDevice skew is measured between outputs under identical transitions and conditions on any one device.
25.Devicetodevice skew for identical transitions at identical VCC levels.
26.VINPP (MAX) cannot exceed VCC VEE (applicable only when VCCVEE < 2600 mV).
27.Additive RMS Jitter with 50% duty cycle clock signal at 10 GHz.
28.Additive PeaktoPeak data dependent jitter with NRZ PRBS 2311 data at 10 Gb/s.
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