参数资料
| 型号： | NBSG86AMNR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 2/17页 |
| 文件大小： | 0K |
| 描述： | IC SMART GATE SIGE DIFF 16QFN |
| 产品变化通告： | LTB Notification 06/Feb/2008 |
| 标准包装： | 3,000 |
| 逻辑类型： | 可配置多功能 |
| 电路数： | 2 |
| 输入数： | 2 |
| 施密特触发器输入： | 无 |
| 输出类型： | 差分 |
| 电源电压： | 2.375 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-VFQFN 裸露焊盘 |
| 供应商设备封装： | 16-QFN（3x3） |
| 包装： | 带卷 (TR) |
| 其它名称： | NBSG86AMNR2OSTR |
NBSG86A
http://onsemi.com
10
Table 13. AC CHARACTERISTICS
VCC = 0 V; VEE = 3.465 V to 2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V
Symbol
Characteristic
40°C
25°C
85°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fmax
Maximum Input Clock Frequency
7
8
7
8
7
8
GHz
VOUTPP Output Voltage Amplitude
fin v 7 GHz
(OLS = VCC)fin = 8 GHz
590
270
730
440
470
230
720
420
540
180
700
390
mV
tPLH,
tPHL
Propagation Delay to Output Differential
(Figure 16)
D/SEL → Q
110
160
210
115
165
215
120
170
220
ps
tSKEW
Duty Cycle Skew (Note 27)
5
15
5
15
5
15
ps
tSKEW
Channel Skew
Q → D/SEL
5
20
5
20
5
20
ps
tS
SetUp Time (Dx to SEL)
30
ps
tH
HoldUp Time (Dx to SEL)
35
ps
tJITTER
RMS Random Clock Jitter
fin v 7 GHz
PeaktoPeak Data Dependent Jitter
(Note 30)
fin v 7 Gb/s
0.5
12
1.5
0.5
12
1.5
0.5
12
1.5
ps
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 28)
75
2600
75
2600
75
2600
mV
tr
tf
Output Rise/Fall Times (20% 80%)
(Q, Q)
tr
@ 1 GHz
tf
30
17
45
35
60
65
30
17
45
35
60
65
30
17
45
35
60
65
ps
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
26.Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to VCC 2.0 V. Input edge rates 40 ps (20% 80%).
28.VINPP (max) cannot exceed VCC VEE.
29.Additive RMS jitter with 50% duty cycle clock signal at 7 GHz.
30.Additive PeaktoPeak data dependent jitter with NRZ PRBS 2311 data rate at 7 Gb/s.
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