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参数资料
| 型号： | NCP1015ST100T3G |
| 厂商： | ON Semiconductor |
| 文件页数： | 13/22页 |
| 文件大小： | 0K |
| 描述： | IC OFFLINE SWIT SMPS CM SOT223 |
| 标准包装： | 1 |
| 输出隔离： | 隔离 |
| 频率范围： | 90kHz ~ 110kHz |
| 输入电压： | 8.1 V ~ 10 V |
| 输出电压： | 700V |
| 功率（瓦特）： | 19W |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | TO-261-4，TO-261AA |
| 供应商设备封装： | SOT-223 |
| 包装： | 标准包装 |
| 其它名称： | NCP1015ST100T3GOSDKR |
NCP1015
Soft ? Start
The NCP1015 features an internal 1 ms soft ? start
activated during the power on sequence (P ON ). As soon as
V CC reaches V CC(off) , the peak current is gradually
increased from nearly zero up to the maximum internal
clamping level (e.g. 350 mA). This situation lasts 1 ms and
further to that time period, the peak current limit is blocked
to the maximum until the supply enters regulation. The
V CC
0 V (Fresh PON)
or
4.7 V (Overload)
Current
soft ? start is also activated during the over current burst
(OCP) sequence. Every re ? start attempt is followed by a
soft ? start activation. Generally speaking, the soft ? start will
be activated when V CC ramps up either from zero (fresh
power ? on sequence) or 4.5 V, the latch ? off voltage
occurring during OCP. Figure 21 shows the soft ? start
behavior. The time scales are purposely shifted to offer a
better zoom portion.
8.5 V
Max Ip
Sense
1.0 ms
Figure 21. Soft ? Start is Activated During a Start ? up Sequence or an OCP Condition
Non ? latching Shutdown
In some cases, it might be desirable to shut off the part
temporarily and authorize its re ? start once the default has
disappeared. This option can easily be accomplished
through a single NPN bipolar transistor wired between FB
and ground. By pulling FB below the internal skip level
(V skip ), the output pulses are disabled. As soon as FB is
relaxed, the IC resumes its operation. Figure 22 shows the
application example:
1
2
3
8
7
4
5
Transformer
ON/OFF
+
CV CC
Figure 22. A Non ? latching Shutdown where Pulses are Stopped as long as the NPN is Biased
Full Latching Shutdown
Other applications require a full latching shutdown, e.g.
when an abnormal situation is detected (over temp or
overvoltage). This feature can easily be implemented
through two external transistors wired as a discrete SCR.
When the OVP level exceeds the zener breakdown voltage,
the NPN biases the PNP and fires the equivalent SCR,
permanently bringing down the FB pin. The switching
pulses are disabled until the user un ? plugs the power supply.
http://onsemi.com
13
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