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| 型号： | NCP1028LEDGEVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 20/29页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR NCP1028LEDG |
| 设计资源： | NCP1028LEDGEVB BOM CP1028LEDGEVB Gerber Files NCP1028LED EVB Schematic |
| 标准包装： | 1 |
| 电流 - 输出 / 通道： | 720mA |
| 输出及类型： | 1，隔离 |
| 输出电压： | 18V |
| 输入电压： | 90 ~ 265VAC |
| 已供物品： | 板 |
| 已用 IC / 零件： | NCP1028 |
| 其它名称： | NCP1028LEDGEVBOS |
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NCP1028
As the internal logic takes some time to react, the switch
gate shutdown does not immediately occur when the
maximum power limit is detected (just before activating
the overload protection circuit). Clearly speaking, it can
take up to 100 ns for the NCP1028 current sense
comparator to propagate through the various logical gates
before reaching the power switch and finally shutting it off.
This is the well-known propagation delay noted t prop .
Unfortunately, during this time, the current keeps growing
as Figure 35 depicts. The peak current will therefore be
> 30 ms
troubled by this propagation delay. The formula to obtain
the final value is simply:
Ipeak, final + in t prop ) Ipeak, max
Figure 34. The burst frequency becomes so low
V
Lp
(eq. 5)
that it is difficult to keep an adequate level on the
auxiliary V CC .
Over Power Compensation
Over Power Compensation or Protection (OPP)
represents a way to limit the effects of the propagation
delay when the converter is supplied from its highest input
voltage. The propagation delay naturally extends the
power capability of any current-limited converter.
Figure 35 explains why. The main parameter is the on
slope, that is to say, the pace at which the inductor current
grows-up when the power switch closes. For a flyback
At low line, S on is relatively low and does not bother the
final peak value. The situation differs at high line and
induces a higher peak current. Therefore, the power supply
output power capability increases with the input voltage.
Let us a take a look at a simple example. Suppose the peak
current is 700 mA:
L p = 1.0 mH
V in lowline = 100 Vdc
V in highline = 350 Vdc
I peak,max = 700 mA
t prop = 100 ns
Pout + 1 I2peak, final FSWLp h
controller, the slope is given by:
2
(eq. 6)
Son + in
V
Lp
(eq. 4)
Where: F sw is the switching frequency and h the efficiency.
Usually h is bigger in high line conditions than in low line
where L p
is the transformer magnetizing/primary
conditions. This formula is valid for a Discontinuous
inductance and V in , the input voltage.
Conduction Mode flyback.
From Equation 5, we can calculate the final peak current
in both conditions:
I peak,final = (100/1m) x 100n + 700m = 710 mA at low line.
I peak,final = (350/1m) x 100n + 700m = 735 mA at high line.
From Equation 6, we can have an idea of the maximum
output power capability again, in both conditions with
respective low and high line efficiency numbers of 78%
and 82% for instance:
P out,lowline = 0.5
P out,highline = 0.5
0.71 2
0.735 2
1m
1m
65k
65k
0.78 = 12.8 W
0.82 = 14.4 W
Figure 35. Internal logic blocks take a certain
amount of time before shutting off the driving
pulses in presence of an overcurrent event.
http://onsemi.com
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