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参数资料
| 型号： | NCP1230P65G |
| 厂商： | ON Semiconductor |
| 文件页数： | 13/21页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM SMPS OVP OCP 7DIP |
| 标准包装： | 50 |
| 输出隔离： | 隔离 |
| 频率范围： | 65kHz |
| 输入电压： | 8.4 V ~ 18 V |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 8-DIP（0.300"，7.62mm），7 引线 |
| 供应商设备封装： | 7-PDIP |
| 包装： | 管件 |
NCP1230
NCP1230 confirms that the low output power condition is
present, and the internal SW1 opens, and the PFC_Vcc
signal output is shuts down. While the NCP1230 is in the
skip mode the FB pin will move around the 750 mV
threshold level, with approximately 100 mVp ? p of
hysteresis on the skip comparator, at a period which depends
upon the (light) loading of the power supply and its various
time constants. Since this ripple amplitude superimposed
over the FB pin is lower than the second threshold (1.25
volt), the PFC_Vcc comparator output stays high (PFC_Vcc
output Pin 1 is low).
In Phase four , the output power demands have increases
and the feedback voltage rises above the 1.25 volts
threshold, the NCP1230 exits the skip mode, and returns to
normal operation.
Max I P
Regulation
Ramp Compensation
In Switch Mode Power Supplies operating in Continuous
Conduction Mode (CCM) with a duty ? cycle greater than
50%, oscillation will take place at half the switching
frequency. To eliminate this condition, Ramp Compensation
can be added to the current sense signal to cure sub harmonic
oscillations. To lower the current loop gain one typically
injects between 50 and 100% of the inductor down slope.
The NCP1230 provides an internal 2.3 Vpp ramp which
is summed internally through a 18 k W resistor to the current
sense pin. To implement ramp compensation a resistor needs
to be connected from the current sense resistor, to the current
sense pin 3.
Example:
If we assume we are using the 65 kHz version of the
NCP1230, at 65 kHz the dv/dt of the ramp is 130 mV/ m s.
Assuming we are designing a FLYBACK converter which
has a primary inductance, Lp, of 350 m H, and the SMPS has
a +12 V output with a Np:Ns ratio of 1:0.1. The OFF time
primary current slope is given by:
(Vout ) Vf) @ Np = 371 mA/ m s or 37 mV/ m s
V FB
1.25 V
0.75 V
Skip + 60%
Ns
Lp
when imposed on a current sense resistor (Rsense) of 0.1 W .
If we select 75% of the inductor current downslope as our
PFC is On
Rcomp + 18k @ divratio = 4.69 k W
PFC is Off
PFC is Off
125 ms
Delay
Figure 32.
No Delay
PFC is On
required amount of ramp compensation, then we shall inject
27 mV/ m s.
With our internal compensation being of 130 mV, the
divider ratio ( divratio ) between Rcomp and the 18 k W is
0.207. Therefore:
(1 * divratio)
Leaving Standby (Skip Mode)
When the feedback voltage rises above the 1.25 volts
reference (leaving standby) the skip cycle activity stops and
SW1 immediately closes and restarts the PFC, there is no
delay in turning on SW1 under these conditions, refer to
Figure 32.
2.3 V
0V
Current Sense
The NCP1230 is a peak current mode controller, where
the current sense input is internally clamped to 1.0 V, so the
sense resister is determined by Rsense = 1.0 V /Ipk
LEB
18 k
CS
Rcomp
Rsense
maximum.
There is a 18k resistor connected to the CS pin, the other
end of the 18k resistor is connect to the output of the internal
oscillator for ramp compensation (refer to Figure 33).
http://onsemi.com
13
Fb/3
Figure 33.
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相关代理商/技术参数 |
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| NCP1231 | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:Low−Standby Power High Performance PWM Controller |
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