参数资料
型号: NCP1234AD65R2G
厂商: ON Semiconductor
文件页数: 27/33页
文件大小: 0K
描述: IC REG CTRLR FLYBACK PWM 7SOIC
标准包装: 2,500
PWM 型: 电流模式
输出数: 1
频率 - 最大: 70kHz
占空比: 85%
电源电压: 9.5 V ~ 28 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)7 引线
包装: 带卷 (TR)
NCP1234
V FB
V FB(fold)
V skip(out)
V skip(in)
Exits
skip
Exits
Time
Enters
skip
Enters
skip
skip
DRV
Time
Figure 45. Skip Cycle Timing Diagram
Latch ? off Input
VDD
I NTC
+
+
?
V OVP
blanking
t Latch(OVP)
I NTC
Latch
1 k W
+
?
+
V OTP
blanking
t Latch(OTP)
S
Q
R
Latch
V clamp
Soft ? start
end
Figure 46. Latch Detection Schematic
Reset
The Latch pin is dedicated to the latch ? off function: it
includes two levels of detection that define a working
window, between a high latch and a low latch: within these
two thresholds, the controller is allowed to run; but as soon
as either the low or the high threshold is crossed, the
controller is latched off. The lower threshold is intended to
be used with an NTC thermistor, thanks to an internal current
source I NTC .
An active clamp prevents the voltage from reaching the
high threshold if it is only pulled up by the I NTC current. To
reach the high threshold, the pull ? up current has to be higher
than the pull ? down capability of the clamp (typically
1.5 mA at V OVP ).
To avoid any false triggering, spikes shorter than 50 m s
(for the high latch and 65 kHz version) or 350 m s (for the low
latch) are blanked and only longer signals can actually latch
the controller.
Reset occurs when V CC is cycled down to a reset voltage,
which in a real application can only happen if the power
supply is unplugged from the AC line.
Upon start ? up, the internal references take some time
before being at their nominal values; so one of the
comparators could toggle even if it should not. Therefore the
internal logic does not take the latch signal into account
before the controller is ready to start: once V CC reaches
V CC(on) , the latch pin High latch state is taken into account
http://onsemi.com
27
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