参数资料
型号: NCP1234BD100R2G
厂商: ON Semiconductor
文件页数: 20/33页
文件大小: 0K
描述: IC REG CTRLR FLYBACK PWM 7SOIC
标准包装: 2,500
PWM 型: 电流模式
输出数: 1
频率 - 最大: 108kHz
占空比: 85%
电源电压: 9.5 V ~ 28 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)7 引线
包装: 带卷 (TR)
NCP1234
I P
I P to be
I LIMIT
High
compensated
Line
t delay
t delay
Low
Line
time
Figure 34. Line Compensation for True Overpower Protection
To compensate this and have an accurate overpower
protection, an offset proportional to the input voltage is
added on the CS signal by turning on an internal current
source: by adding an external resistor in series between the
sense resistor and the CS pin, a voltage offset is created
across it by the current. The compensation can be adjusted
by changing the value of the resistor.
But this offset is unwanted to appear when the current
sense signal is small, i.e. in light load conditions, where it
HV
(32 ms)
Watch
Dog
V HVstop
A/D 3 bit
would be in the same order of magnitude. Therefore the
compensation current is only added when the FB voltage is
higher than V FB(OPCE) .
However, because the HV pin can be connected to an ac
voltage, there is needed an additional circuitry to read or at
least closely estimate the actual voltage on the bulk
capacitor.
Converter
+
Peak Detector
3 bit
Register
I Generator
I ctrl
FB
To CS
Block
T blanking
LEB
CS
V FB (OPC)
Figure 35. Schematic Overpower Compensation Circuit
A 3 bit A/D converter with the peak detector senses the ac
input, and its output is periodically sampled and reset, in
order to follow closely the input voltage variations. The
sample and reset events are given by the V HVsample
comparator used for sampling detection for the AC line
input. If only the DC high voltage input is used, no reset
signal is generated by the V HVsample condition and the 32 ms
watch dog is used to generate the sampling events for
sampling the DC input high voltage line.
http://onsemi.com
20
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