参数资料
| 型号： | NCP1294EDR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 10/13页 |
| 文件大小： | 0K |
| 描述： | IC PWM CTLR FLYBACK 16SOIC |
| 标准包装： | 2,500 |
| 输出隔离： | 隔离 |
| 频率范围： | 260kHz ~ 320kHz |
| 输入电压： | 4.7 V ~ 15 V |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC N |
| 包装： | 带卷 (TR) |
NCP1294
DESIGN GUIDELINES
Switch Frequency and Maximum Duty Cycle
Calculations
Oscillator timing capacitor, C T , is charged by V REF
through R T and discharged by an internal current source.
During the discharge time, the internal clock signal sets the
Gate output to the low state, thus providing a user selectable
maximum duty cycle clamp. Charge and discharge times are
determined by following general formulas;
tC + RTCT ln
(VREF * VVALLEY)
(VREF * VPEAK)
td + RTCT ln
where:
(VREF * VPEAK * IdRT)
(VREF * VVALLEY * IdRT)
Figure 8. The SYNC Pin Generates a Sync Pulse at
the Beginning of Each Switching Cycle.
CH2: GATE Pin, CH3: R T C T , CH4: SYNC Pin
t C = charging time;
t d = discharging time;
V VALLEY = valley voltage of the oscillator;
V PEAK = peak voltage of the oscillator.
Substituting in typical values for the parameters in the
above formulas, V REF = 3.3 V, V VALLEY = 1.0 V, V PEAK =
2.0 V, I d = 1.0 mA:
tC + 0.57RTCT
td + RTCT ln
1.3 * 0.001RT
2.3 * 0.001RT
0.57 ) In 1.3 * 0.001RT
D max +
0.57
T
It is noticed from the equation that for the oscillator to
function properly, R T has to be greater than 2.3 k.
Select RC for Feed Forward Ramp
If the line voltage is much greater than the FF pin Peak
Voltage, the charge current can be treated as a constant and
is equal to V IN /R. Therefore, the volt ? second value is
determined by:
VIN
TON + (VCOMP * VFF(d))
R
C
VIN
TON +
Figure 9. Operation with External Sync.
CH2: SYNC Pin, CH3: GATE Pin, CH4: R T C T Pin
An external pulse signal can feed to the bidirectional
SYNC pin to synchronize the switch frequency. For reliable
operation, the sync frequency should be approximately 20%
higher than free running IC frequency. As show in Figure 9,
when the SYNC pin is triggered by an incoming signal, the
IC immediately discharges C T . The GATE signal is turned
on once the R T C T pin reaches the valley voltage. Because of
the steep falling edge, this valley voltage falls below the
regular 1.0 V threshold. However, the R T C T pin voltage is
then quickly raised by a clamp. When the R T C T pin reaches
the 0.95 V (typ) Valley Clamp Voltage, the clamp is
disconnected after a brief delay and C T is charged through
R T .
where:
V COMP = COMP pin voltage;
V FF(d) = FF pin discharge voltage.
As shown in the equation, the volt ? second clamp is set by
the V COMP clamp voltage which is equal to 1.8 V. In
Forward or Flyback circuits, the volt ? second clamp value is
designed to prevent transformers from saturation.
In a buck or forward converter, volt ? second is equal to
VOUT TS
n
n = transformer turns ratio, which is a constant determined
by the regulated output voltage, switching period and
transformer turns ration (use 1.0 for buck converter). It is
interesting to notice from the aforementioned two equations
http://onsemi.com
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