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参数资料
| 型号： | NCP1351CDR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 16/27页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM PROG CM OTP 8SOIC |
| 标准包装： | 2,500 |
| 输出隔离： | 隔离 |
| 频率范围： | 调节 |
| 输入电压： | 9.5 V ~ 28 V |
| 工作温度： | -25°C ~ 125°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 带卷 (TR) |
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NCP1351
V CC
I timer
10 m
V CC
D aux
Timer
C timer
100nF
V CC
+
V timer
5
+
-
S
Q
Q
20 m s
Filter
CV CC
I CC
to DRV
+
L aux
Stage
P on
R
FB
Reset
I FB
I FB
+
-
+
C1
100n
R1
2.5k
D FB
I FB
I FB < 40 m A ? = Low
Else = High
V CC ==
VCC (min)
? Reset
DRV Pulses
Auto-Recovery - B Version
V CC
C timer
100nF
Timer
I timer
10 m
+
V timer
+
-
20 m s
Filter
6V
V CC
CV CC
I CC
+
D aux
L aux
V CC
P on
5
FB
Reset
I FB
I FB
+
-
+
SCR Delatches When
I SCR < ICC latch (Few m A)
C1
100n
R1
2.5k
D FB
I FB
I FB < 40 m A ? = Low
Else = High
Latched - A Version
Figure 19. The Internal Fault Management Differs Depending on the Considered Version
Knowing both the ending voltage and the charge current,
we can easily calculate the timer capacitor value for a given
delay. Suppose we need 40 ms. In that case, the capacitor is
simply:
designer select a 100 kHz maximum switching frequency,
then the error flag would raise and start the timer for an
operating frequency above ≈ 50 kHz. Below 50 kHz, the
timer pin remains grounded. If we consider a DCM
Ctimer + timer +
I T
Vtimer
11.7 m
5
40 m
+ 94 nF
(eq. 16)
operation at full load, as the inductor peak current is kept
constant, these 50 kHz correspond to 50% of the maximum
delivered power. If the load stays between 50% and 100% of
Select a 100 nF value.
To let the designer understand the behavior behind the
four different options (A, B, C and D), we have graphed
important signals during a fault condition. In versions A and
B, an internal error flag is raised as soon the controller hits
the maximum operating frequency. At this moment, the
external timer capacitor charge begins. If the fault persists,
the timer capacitor hits the fault level and the circuit is either
latched (A) or enters auto-recovery burst mode (B). If the
fault disappears, the timer capacitor is simply reset to 0 V by
an internal switch.
On version C and D, the error flag is asserted as soon as
the current feedback imposes a switching frequency roughly
its nominal value, the timer continues to charge until it
reaches the final level. In that case, the circuit latches off (C)
or enters auto-recovery (D). This behavior is particularly
well suited for applications where the converter delivers a
moderate average power but is subjected to sudden peak
loading conditions. For instance, a power supply is designed
to permanently deliver 20 W but is sized to deliver 80 W in
peak conditions. During these 80 W power excursions, the
timer will react but will not shut down the power supply. On
the contrary, if a short-circuit appends or if the transient
overload lasts too long, the timer will immediately start to
further shutdown the controller in order to protect both the
application and downstream load.
equal to half of the maximum limit. For instance, should the
http://onsemi.com
16
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