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参数资料
| 型号： | NCP1351LEDGEVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 19/27页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR NCP1351LEDG |
| 设计资源： | NCP1351 EVB BOM NCP1351LEDGEVB Gerber Files NCP1351LED EVB Schematic |
| 标准包装： | 1 |
| 电流 - 输出 / 通道： | 700mA |
| 输出及类型： | 1，隔离 |
| 输出电压： | 33V |
| 特点： | 短路保护 |
| 输入电压： | 85 ~ 265 V |
| 已供物品： | 板 |
| 已用 IC / 零件： | NCP1351 |
| 其它名称： | NCP1351LEDGEVBOS |
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NCP1351
Latch Input
The NCP1351 features a patented circuitry which
prevents the FB input to be of low impedance before the V CC
reaches the VCC ON level. As such, the circuit can work in
a primary regulation scheme. Capitalizing on this typical
V CC
OVP
D2
option, Figure 24 shows how to insert a zener diode in series
with the optocoupler emitter pin. In that way, the current
5V
FB
Latch
biases the zener diode and offers a nice reference voltage,
appearing at the loop closure (e.g. when the output reaches
the target). Yes, you can use this reference voltage to supply
C2
100n
R1
2.5k
C1
100nF
R pulldown
C3
100nF
a NTC and form a cheap OTP protection.
Figure 24. The Latch Input Offers Everything Needed
to Implement an OTP Circuit. Another Zener Can
Help combining an OVP Circuit if Necessary
V CC
V CC
Aux
OUT
CV CC
20 m F
L aux
R4
2.2k
U1B
+
CV CC
22 m F
Sec
+
U1A
D2
Latch
R OVP
1N4937
Latch
R pulldown
C3
100nF
C4
100n
C5
1n
C1
100nF
D4
Figure 25. You can either directly observe the V CC level or add a small RC filter to reduce the leakage inductance
contribution. The best is to directly sense the output voltage and reacts if it runs away, as offered on the right
side.
Design Example, a 19 V / 3 A
A Universal Mains Power Supply Designing a
Switch-Mode Power Supply using the NCP1351 does not
differ from a fixed frequency design. What changes,
Vds_max + 600 0.85 + 510 V (eq. 17)
Knowing a maximum bulk voltage of 375 V, the clamp
voltage must be set to:
however, is the regulation method via frequency variations.
Vclamp + 510 * 375 + 135 V
(eq. 18)
Vout ) V f Vclamp
+
In other words, all the calculations must be carried at the
lowest line input where the frequency will hit the maximum
value set by the C t capacitor. Let us follow the steps:
V in min = 100 Vdc (bulk valley in low-line conditions)
V in max = 375 Vdc
V out = 19 V
I out = 3 A
Operating mode is CCM
h = 0.8
F sw = 65 kHz
Based on the above level, we decide to adopt a headroom
between the reflected voltage and the clamp level of 50 V. If
this headroom is too small, a high dissipation will occur on
the RDC clamp network and efficiency will suffer. A
leakage inductance of around 1% of the magnetizing value
should give good results with this choice (k c = 1.6). The turn
ratio between primary and secondary is simply:
(eq. 19)
N kc
Ns kC Vout ) V f
1. Turn Ratio. This is the first parameter to consider.
The MOSFET BV dss actually dictates the amount
of reflected voltage you need. If we consider a
600 V MOSFET and a 15% derating factor, we
must limit the maximum drain voltage to:
Solving for N gives:
N + +
Np Vclamp
+ 0.234
+
1.6
(19 ) 0.8)
135
(eq. 20)
http://onsemi.com
19
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| NCP1351PRINTGEVB | 功能描述:电源管理IC开发工具 NCP1351 40 W PRINTER EVB RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
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