参数资料
型号: NCP1529MUTBG
厂商: ON Semiconductor
文件页数: 10/16页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 1A 6UDFN
标准包装: 1
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.9 V ~ 3.9 V
输入电压: 2.7 V ~ 5.5 V
PWM 型: 电流模式
频率 - 开关: 1.7MHz
电流 - 输出: 1A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 6-UDFN 裸露焊盘
包装: 标准包装
供应商设备封装: 6-uDFN(2x2)
其它名称: NCP1529MUTBGOSDKR
NCP1529
DC/DC OPERATION DESCRIPTION
Detailed Description
The NCP1529 uses a constant frequency, current mode
step ? down architecture. Both the main (P ? channel
MOSFET) and synchronous (N ? channel MOSFET)
switches are internal.
The output voltage is set by an external resistor divider in
the range of 0.9 V to 3.9 V and can source at least 1A.
The NCP1529 works with two modes of operation;
PWM/PFM depending on the current required. In PWM
mode, the device can supply voltage with a tolerance of
$ 3% and 90% efficiency or better. Lighter load currents
cause the device to automatically switch into PFM mode to
reduce current consumption and extended battery life.
Additional features include soft ? start, undervoltage
protection, current overload protection and thermal
shutdown protection. As shown on Figure 1, only six
external components are required. The part uses an internal
reference voltage of 0.6 V. It is recommended to keep
NCP1529 in shutdown mode until the input voltage is 2.7 V
or higher.
PWM Operating Mode
In this mode, the output voltage of the device is regulated
by modulating the on ? time pulse width of the main switch
Q1 at a fixed 1.7 MHz frequency.
The switching of the PMOS Q1 is controlled by a flip ? flop
driven by the internal oscillator and a comparator that
compares the error signal from an error amplifier with the
sum of the sensed current signal and compensation ramp.
The driver switches ON and OFF the upper side transistor
(Q1) while the lower side transistor is switched OFF then
ON.
At the beginning of each cycle, the main switch Q1 is
turned ON by the rising edge of the internal oscillator clock.
The inductor current ramps up until the sum of the current
sense signal and compensation ramp becomes higher than
the error amplifier ’s voltage. Once this has occurred, the
PWM comparator resets the flip ? flop, Q1 is turned OFF
while the synchronous switch Q2 is turned ON. Q2 replaces
the external Schottky diode to reduce the conduction loss
and improve the efficiency. To avoid overall power loss, a
certain amount of dead time is introduced to ensure Q1 is
completely turned OFF before Q2 is being turned ON.
V OUT
I SW
V SW
Figure 26. PWM Switching Waveforms
(V IN = 3.6 V, V OUT = 1.2 V, I OUT = 600 mA,
Temperature = 25 5 C)
PFM Operating Mode
Under light load conditions, the NCP1529 enters in low
current PFM mode of operation to reduce power
consumption. The output regulation is implemented by
pulse frequency modulation. If the output voltage drops
below the threshold of PFM comparator a new cycle will be
initiated by the PFM comparator to turn on the switch Q1.
Q1 remains ON during the minimum on time of the structure
while Q2 is in its current source mode. The peak inductor
current depends upon the drop between input and output
voltage. After a short dead time delay where Q1 is switched
OFF, Q2 is turned in its ON state. The negative current
detector will detect when the inductor current drops below
zero and sends a signal to turn Q2 to current source mode to
prevent a too large deregulation of the output voltage. When
the output voltage falls below the threshold of the PFM
comparator, a new cycle starts immediately.
V OUT
V SW
I SW
Figure 27. PFM Switching Waveforms
(V IN = 3.6 V, V OUT = 1.2 V, I OUT = 0 mA,
Temperature = 25 5 C)
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