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| 型号： | NCP1578MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 13/22页 |
| 文件大小： | 1861K |
| 描述： | IC REG DL BCK/LINEAR SYNC 20-QFN |
| 产品变化通告： | Product Obsolescence 19/Dec/2008 |
| 标准包装： | 4,000 |
| 拓扑： | 降压（降压）同步（1），线性（LDO）（1） |
| 功能： | 任何功能 |
| 输出数： | 2 |
| 频率 - 开关： | 300kHz |
| 电压/电流 - 输出 1： | 控制器 |
| 电压/电流 - 输出 2： | 5V，50mA |
| 带 LED 驱动器： | 无 |
| 带监控器： | 无 |
| 带序列发生器： | 是 |
| 电源电压： | 4.5 V ~ 24 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-VFQFN 裸露焊盘 |
| 供应商设备封装： | 20-QFN（4x4） |
| 包装： | 带卷 (TR) |
NCP1578
http://onsemi.com
13
DETAILED OPERATING DESCRIPTION
General
The NCP1578 synchronous step-down power controller
contains a PWM controller and a 5 V/50 mA linear regulator
for wide battery/adaptor voltage range applications
The NCP1578 includes power good voltage monitor,
soft-start, over current protection, undervoltage protection,
overvoltage protection, LDO5 UVLO and thermal
shutdown. The NCP1578 allows for improved efficiency at
light loads by allowing the synchronous MOSFET to turn off
automatically making this device a ideal for battery operated
systems. The IC is packaged in QFN20.
Control Logic
The LDO5 is enabled when EN_LDO is high. The PWM
controller is enabled when EN_SW is high. The internal V
ref
is activated whenever the output of LDO5 rises above the
UVLO threshold of 65% of V
FB
volts, power-on reset
occurs which resets all the protection faults. The device's
control logic is powered by LDO5 internally. Once V
ref
reaches its regulation voltage, an internal signal will wake
up the supply undervoltage monitor which will assert a
GOOD condition if LDO5 voltage is within certain preset
levels.
Linear Regulator
The 5 V linear regulator can supply total 50 mA current
for both internal and external loads. It can be enabled or
disabled independently by the control pin EN_LDO. When
EN_LDO = 1, the UVLO voltage is set as 4.5 V with
hystersis 330 mV typical. It is recommended to bypass
LDO5 output with 1 mF (min) ceramic capacitors.
Switching Controller
The controller directly drives two external N-Channel
power FETs. An external resistor divider sets the nominal
output voltage. The control architecture is voltage mode
fixed frequency with input voltage feedforward PWM. The
part is compensated externally. The switching frequency is
fixed at 300 kHz?0%. The SMPS output voltage is divided
down via resistor network and fed back to the inverting input
of an internal error amplifier through FB pin to close the loop
at V
out
. This amplifier compares the feedback voltage with
an internal V
ref
to generate an error signal for the PWM
comparator. This error signal is further compared with a
fixed frequency RAMP waveform derived from the internal
oscillator to generate a pulse-width-modulated signal. This
PWM signal drives the external N-Channel Power FETs via
the TG and BG pins. External inductor and capacitor filter
the output waveform. The SMPS output voltage ramps up at
a pre-defined soft-start rate when the EN_SW pin goes
HIGH from LOW after V
ref
is ready.
Input voltage feedforward is implemented to the RAMP
signal generation to reject the effect of wide input voltage
variation. With input voltage feedforward, the amplitude of
the RAMP is proportional to the input voltage.
For enhanced efficiency, an active synchronous switch is
used to eliminate the conduction loss contributed by the
forward voltage of a Schottky diode rectifier. Adaptive
nonoverlap timing control of the complementary gate drive
output signals is provided to reduce large shoot-through
current that degrades efficiency.
When the forced PWM is disabled, the low-side
MOSFET is allowed to turn off after the detection of
negative inductor current.
Overcurrent Protection of SMPS Controllers
An external resistor connected between the input voltage
and OCSET sets the current limit for the high-side switch.
An internal 40 mA current sink (IOC) at OCSET pin
establishes a voltage drop across this resistor and develops
a voltage at input and is compared to the voltage at SWN pin
when the high-side gate drive is high after a fixed period of
blanking time (X150 ns) to avoid false current limit
triggering. When the voltage at SWN is lower than that at the
input for 16 consecutive internal clock cycles, an over
current condition occurs. Those 16 consecutive cycles will
be operating as cycle by cycle condition in the way such that
for each cycle, TG is OFF once the inductor current hits the
preset threshold value. The SMPS output will be latched off
after those 16 cycles to protect against a short-to-ground
condition on SWN or OUT. The IC will be reset once LDO5
or EN_SW is cycled.
Output Voltages Sensing
The SMPS output voltage is sensed across the FB and
AGND pins. FB should be connected through a feedback
resistor divider to the output voltage point of regulation. The
AGND should be connected directly through a sense trace
to the remote ground sense point which is usually the ground
of local bypass capacitor for load.
Supply Voltage Under-Voltage Monitor
The IC continuously monitors LDO5 output pin. The IC
will shutdown if the voltage is below 4.5 V.
Thermal Shutdown
The IC will shutdown if the die temperature exceeds
150_C. The IC restarts operation only after the junction
temperature drops below 125_C.
Power Good
The PGOOD is an open-drain output of a comparator
which continuously monitors SMPS output voltage. The
Power Good time delay can be programmable by connecting
an external capacitor. The PGOOD is true (high impedance)
when the FB pin is within $15% of the preset nominal
regulation voltage. The PGOOD is false (pulled low) when
FB rises above 15% or falls below 15% the nominal
regulation point. PGOOD pin also pulls low when
protection fault occurs (OVP, UVP, OTP, and UVLO), or
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