参数资料
型号: NCP1579DR2G
厂商: ON Semiconductor
文件页数: 9/11页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 8-SOIC
标准包装: 1
PWM 型: 电压模式
输出数: 1
频率 - 最大: 317kHz
占空比: 80%
电源电压: 4.5 V ~ 13.2 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 标准包装
其它名称: NCP1579DR2GOSDKR
NCP1579
Ipk * pk LOUT +
V OUT (1 * D)
L OUT
275 kHz
F LC +
tight output voltage regulation. In contrast, smaller values of
inductance increase the regulator ’s maximum achievable
slew rate and decrease the necessary capacitance, at the
expense of higher ripple current. The peak-to-peak ripple
current for NCP1579 is given by the following equation:
,
where Ipk-pk LOUT is the peak to peak current of the output.
From this equation it is clear that the ripple current increases
as L OUT decreases, emphasizing the trade-off between
dynamic response and ripple current.
Feedback and Compensation
The NCP1579 allows the output of the DC-DC converter
to be adjusted from 0.8 V to 5.0 V via an external resistor
divider network. The controller will try to maintain 0.8 V at
the feedback pin. Thus, if a resistor divider circuit was
placed across the feedback pin to V OUT , the controller will
regulate the output voltage proportional to the resistor
divider network in order to maintain 0.8 V at the FB pin.
V OUT
Figure 10 shows a typical Type II transconductance error
amplifier (EOTA). The compensation network consists of
the internal error amplifier and the impedance networks ZIN
(R 1 , R 2 ) and external Z FB (R c , C c and C p ). The
compensation network has to provide a closed loop transfer
function with the highest 0 dB crossing frequency to have
fast response (but always lower than F SW /8) and the highest
gain in DC conditions to minimize the load regulation. A
stable control loop has a gain crossing with -20 dB/decade
slope and a phase margin greater than 45 ° . Include
worst-case component variations when determining phase
margin. Loop stability is defined by the compensation
network around the EOTA, the output capacitor, output
inductor and the output divider. Figure 11 shows the open
loop and closed loop gain plots.
Compensation Network Frequency:
The inductor and capacitor form a double pole at the
frequency
1
2 p L o C o
The ESR of the output capacitor creates a “zero” at the
frequency,
R1
FB
F ESR +
2 p
1
ESR
C o
F Z +
V REF
V OUT * V REF
F p +
R2
The relationship between the resistor divider network above
and the output voltage is shown in the following equation:
R 2 + R 1
Resistor R1 is selected based on a design tradeoff between
efficiency and output voltage accuracy. For high values of
R1 there is less current consumption in the feedback
network, However the trade off is output voltage accuracy
due to the bias current in the error amplifier. The output
voltage error of this bias current can be estimated using the
following equation (neglecting resistor tolerance):
The zero of the compensation network is formed as,
1
2 p R c C c
The pole of the compensation network is calculated as,
1
2 p R c C p
Error% +
0.1 m A
V REF
R 1
100%
Once R1 has been determined, R2 can be calculated.
Figure 11. Gain Plot of the Error Amplifier
R 1
C c
R c
C p
EA
Gm
V ref
+
?
R 2
Thermal Considerations
The power dissipation of the NCP1579 varies with the
MOSFETs used, V CC , and the boost voltage (V BST ). The
average MOSFET gate current typically dominates the
control IC power dissipation. The IC power dissipation is
determined by the formula:
Figure 10. Type II Transconductance Error
Amplifier
Where:
P IC + (I CC
V CC ) ) P TG ) P BG
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