参数资料
型号: NCP1595MNT2G
厂商: ON Semiconductor
文件页数: 12/13页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 1.5A 6DFN
标准包装: 3,000
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 可调至 0.8V
输入电压: 4 V ~ 5.5 V
PWM 型: 电流模式
频率 - 开关: 1MHz
电流 - 输出: 1.5A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 6-VDFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 6-DFN(3x3)
NCP1595, NCP1595A, NCP1595C
Calculate the power lost in the NCP1595/A/C using the
following equations:
1. High side MOSFET
q JC is the junction ? to ? case thermal resistance equal to
1.7 ° C/W. T C is the temperature of the case and TJ is the
junction temperature, or die temperature. The
P HSON + I
R DS(on)HS
The conduction loss in the top switch is:
2
RMS_HSFET
(eq. 8)
case ? to ? ambient thermal resistance is dependent on how
well heat can be transferred from the PC board to the air.
Solder the underside ? exposed pad to a large copper GND
Where:
I RMS_FET +
I out 2 )
D I PP
12
2
D
(eq. 9)
plane. If the die temperature reaches +185 ° C the
NCP1595/A/C shut down and does not restart again until the
die temperature cools by 40 ° C.
Layout Consideration
D I PP is the peak ? to ? peak inductor current ripple.
The power lost due to switching the internal power high side
MOSFET is:
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For 1.0MHz
switching frequency, switch rise and fall times are typically
P HSSW +
V in @ I out @ t r ) t f @ f SW
2
(eq. 10)
in few nanosecond range. To prevent noise both radiated and
conducted the high speed switching current path must be
kept as short as possible. Shortening the current path will
t r and t f are the rise and fall times of the internal power
MOSFET measured at SW node.
2. Low side MOSFET
The power dissipated in the top switch is:
P LSON + I RMS_LSFET 2 @ R DS(on)LS (eq. 11)
Where:
also reduce the parasitic trace inductance of approximately
25 nH/inch. At switch off, this parasitic inductance
produces a flyback spike across the NCP1595/A/C switch.
When operating at higher currents and input voltages, with
poor layout, this spike can generate voltages across the
NCP1595/A/C that may exceed its absolute maximum
rating. A ground plane should always be used under the
switcher circuitry to prevent interplane coupling and overall
I RMS_LSFET +
I out 2 )
D I PP
12
2
@ (1 * D )
(eq. 12)
noise.
The FB component should be kept as far away as possible
from the switch node. The ground for these components
D I PP is the peak ? to ? peak inductor current ripple.
The switching loss for the low side MOSFET can be
ignored.
The power lost due to the quiescent current (I Q ) of the device
is:
P Q + V in @ I Q (eq. 13)
I Q is the switching quiescent current of the NCP1595/A/C.
P TOTAL + P HSON ) P HSSW ) P LSON ) P Q (eq. 14)
Calculate the temperature rise of the die using the following
equation:
should be separated from the switch current path. Failure to
do so will result in poor stability or subharmonic like
oscillation.
Board layout also has a significant effect on thermal
resistance. Reducing the thermal resistance from ground pin
and exposed pad onto the board will reduce die temperature
and increase the power capability of the NCP1595/A/C. This
is achieved by providing as much copper area as possible
around the exposed pad. Adding multiple thermal vias under
and around this pad to an internal ground plane will also
help. Similar treatment to the inductor pads will reduce any
additional heating effects.
T J + T C ) P TOTAL @ q JC
(eq. 15)
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