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参数资料
| 型号： | NCP1605FORWGEVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 13/19页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR NCP1605FORWG |
| 设计资源： | NCP1605FORWGEVB BOM NCP1605FORWGEVB Gerber Files NCP1605 EVB Schematic |
| 标准包装： | 1 |
| 主要目的： | AC/DC，主面和辅面，带 PFC |
| 输出及类型： | 1，隔离 |
| 输出电压： | 19V |
| 电流 - 输出： | 8A |
| 输入电压： | 90 ~ 265VAC |
| 稳压器拓扑结构： | 正向转换器 |
| 频率 - 开关： | 133kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | NCP1217，NCP1605 |
| 其它名称： | NCP1605FORWGEVBOS |
NCP1217, NCP1217A
V CC
The startup current source keeps the
VCC ON = 12.8 V
VCC min = 7.6 V
device latched until reset occurs.
VCC latch = 5.6 V
Drv
Reset level
Time
Adj
Driver
Pulses
Latched--off
Time
Default
adj level
Fault brings adj above latching level
Time
Figure 24. When Vadj is Pulled Above 3.1 V, NCP1217 Permanently Latches--Off the Output Pulses
In normal operation, the Adj pin level is kept at a fixed
level, the default one or lower. As soon as some external
signal pulls this Adj pin level above 3.1 V typical, the output
pulses are permanently disabled. Care must be taken to limit
the injected current into pin 1 to less than 2.0 mA, e.g.
Vaux
through a series resistor of 5.6 k with a 10 V V CC . The
startup switch is activated every time V CC reaches 5.6 V and
maintains a V CC voltage ramping up and down between
5.6 V and 12.8 V. Reset occurs when V CC falls below 5.6 V,
e.g. when the user cycle the SMPS down. Figure 25
illustrates the operation. Adding a zener diode from Q1 base
to ground makes a cheap OVP, protecting the supply from
any lethal open--loop operation. If a thermistor (NTC) is
T
OVP
1
2
3
4
8
7
6
5
< 16 V
CV CC
Laux
added in parallel with the Zener--diode, overtemperature
protection is also ensured.
Figure 25. A Thermistor and a Zener Diode Offer
Both OVP and Overtemperature Latched--Off
Protection
Nonlatching Shutdown
In some cases, it might be desirable to shut off the part
temporarily and authorize its restart once the default has
disappeared. This option can easily be accomplished
through a single NPN bipolar transistor wired between FB
and ground. By pulling FB below the Adj Pin 1 level, the
output pulses are disabled as long as FB is pulled below
Pin 1. As soon as FB is relaxed, the IC resumes its operation.
Figure 26 depicts the application example.
http://onsemi.com
13
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