参数资料
| 型号： | NCP3122MNTXG |
| 厂商： | ON Semiconductor |
| 文件页数： | 13/42页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 2A DL 32QFN |
| 产品变化通告： | NCP312x Soft Start Charge 6/Nov/2008 |
| 标准包装： | 4,000 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 2 |
| 输出电压： | 可调至 0.8V |
| 输入电压： | 4.5 V ~ 15 V |
| 频率 - 开关： | 200kHz ~ 2.2MHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 32-QFN（5x5） |
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NCP3122
DETAILED DESCRIPTION
Introduction
The NCP3122 is a dual channel non ? synchronous PWM
voltage mode buck regulator. Each channel is identical and
has a 2.0 A internal P ? FET, compensation, feedback,
programmable soft ? start, enable and power good pins.
These circuits also share the same input voltage, reference
voltage, thermal shutdown, undervoltage detect and master
oscillator. A simple auto ? tracking and sequencing
capability can be implemented using the SEQ/TRACK/SS
pins.
The fixed ? frequency programmable architecture, driven
from a common oscillator, ensures a 180 ° phase differential
between channels. This 180 ° phase shift between the two
channels reduces the common input capacitor requirement
and improves the noise immunity. The NCP3122 switching
frequency is set by an external resistor and is adjustable
between 200 ? 2200 kHz. This allows application
optimization between efficiency and total solution size.
The output voltage is fed back through an external resistor
voltage divider to the FB input pin and compared with the
reference voltage, then the voltage difference is amplified
through the internal transconductance error amplifier. The
output current of the transconductance error amplifier
(OTA) is presented at the COMP node where an RC network
compensates the regulation control system loop.
The NCP3122 features a programmable soft ? start
function, which is implemented through the error amplifier
and the external compensation capacitor. This feature
prevents stress to the power components and limits output
voltage overshoot during start ? up.
Undervoltage Lockout (UVLO)
Undervoltage lockout (UVLO) is provided to ensure that
unexpected behavior does not occur when V in is too low to
support the internal rails and power the converter. In case the
input voltage is higher than the UVLO threshold (4.3 V
standard value, rising voltage), the step down converter
operation can be started. This circuit has a 0.2 V hysteresis
(typical). If the falling trip is activated, switching ceases and
eventually the circuit turns off. When the input circuit is in
this state, the currrent consumption is equal 5 mA (typical).
Fixed Frequency Operation
The NCP3122 uses a constant frequency architecture for
generating a PWM signal. During normal operation, the
oscillator generates an accurate pulse at the beginning of
each switching cycle to turn on the main switch. The main
switch will be turned off when the ramp signal intersects
with the output of the error amplifier (COMP pin voltage).
Therefore, the switch duty cycle can be modified to regulate
the output voltage to the desired value as line and load
conditions change.
The major advantage of fixed frequency operation is that
the component selections, especially the magnetic
component design, become very easy. The oscillator
frequency of the NCP3122 is programmable from 200 kHz
to 2200 kHz using an external resistor connected from the
RT pin to ground. The oscillator works on the double
frequency internally. Therefore, both channels have a 180 °
phase shift of the SW pins.
Out ? of ? Phase Operation
In out ? of ? phase operation, the turn ? on of the second
channel is delayed by half the switching cycle. This delay is
supervised by the oscillator, which supplies a clock signal to
the second channel which is 180 ° out of phase with the clock
signal of the first channel. The advantages of out ? of ? phase
synchronization are many. Since the input current pulses are
interleaved with one another, the overlap time is reduced.
The effect of this overlap reduction is to attenuate the input
filter requirement, allowing the use of smaller components.
Additionally, since peak current occurs during a shorter time
period, emitted EMI is also reduced, thereby reducing
shielding requirements.
Enable Input
Pull the EN enable input high to enable operation. The EN
high signal must occur after VIN has exceeded 2.7 V to
allow internal Power-on Reset (POR) logic to initialize the
IC. Logic low on SEQ forces the NCP3122 into shutdown
mode. Connect SEQ to EN for normal operation of a
standalone device. In shutdown mode, the NCP3122 is
turned off and the supply current is reduced to less than
100 m A. When the enable function is not required, float the
EN connection. The NCP3122 will turn itself on once Vin
crosses the input UVLO threshold. Do not pull EN to VIN
or a separate supply voltage . For standalone operation, EN
should still be connected to SEQ.
Note: For proper operation of the NCP3122 circuit, no
voltage may be pulled high on the output pins. The output
capacitors should be discharged. If this condition is not
observed when NCP3122 is enabled, the regulator does not
start switching. This helps to prevent improper operation of
the NCP3122 circuit due to the implemented tracking and
sequencing features.
Soft ? Start/Stop Control
This capacitor limits the maximum demand on the
external power supply by controlling the inrush current
peaks to charge the output capacitor and DC load and to
attain smoothly increasing output voltage at start ? up. A soft
start circuit forces the error amplifier output to follow a
prescribed voltage ramp when turning on and off. The output
capacitor is discharged when V in goes under the UVLO as
thermal shutdown or overload detection occurs. The circuit
input is presented as a voltage ramp generated by internal
current sources tied to an external SS capacitor. The external
capacitor on the soft ? start node is charged/discharged by the
8.75 m A current from the constant current source, and the
voltage on the SS node controls the OTA amplifier output
http://onsemi.com
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