参数资料
| 型号： | NCP3122MNTXG |
| 厂商： | ON Semiconductor |
| 文件页数： | 19/42页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 2A DL 32QFN |
| 产品变化通告： | NCP312x Soft Start Charge 6/Nov/2008 |
| 标准包装： | 4,000 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 2 |
| 输出电压： | 可调至 0.8V |
| 输入电压： | 4.5 V ~ 15 V |
| 频率 - 开关： | 200kHz ~ 2.2MHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 32-QFN（5x5） |
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NCP3122
Sequencing of Output Voltages
Some microprocessors and DSP chips need two power
supplies with different voltage levels. These systems often
require voltage sequencing between the core power supply
and the I/O power supply. Without proper sequencing,
latch ? up failure or excessive current draw may occur that
could result in damage to the processor’s I/O ports or the I/O
ports of a supporting system device such as memory, an
FPGA or a data converter. To ensure that the I/O loads are
not driven until the core voltage is properly biased, tracking
of the core supply and the I/O supply voltage is necessary.
Designing a system without proper power supply
sequencing for signal processing devices like DSPs, FPGAs,
and PLDs may create risks as to reliability or proper
functionality. The risk comes when there are active and
inactive power supply rails on the device for a long time.
During this time, the ESD structures, internal circuits and
components are stressed from interference between
different voltages (from the two separate power supply
rails). When these conditions persist on multi ? supply
devices for long time periods (this is a cumulative
phenomenon), the life of the products (DSP, FPGA, and
PLD devices) is drastically reduced. The failure is often a
result of high currents flowing to the pins or the high voltage
difference between pins.
In that case, the signal processors require multiple power
supplies generating different voltage levels for core and I/O
peripherals over time. NCP3122 offers ratiometric
sequencing, sequential sequencing and tracking sections to
manage the output voltages behavior during start ? up and
power ? down. Basically, the DSP, FPGA, and PLD
manufacturers do not specify the method of power
sequencing, but they do specify restrictions on the time or
voltage differences during power ? up and power ? down. The
power ? up sequence for microprocessors should be finished
approximately within a few seconds to prevent the risks
mentioned above. For more information, see the
microprocessor manufacturers’ datasheets.
http://onsemi.com
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