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| 型号： | NCP3127CRAGEVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 20/24页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION NCP3127 CERAMIC |
| 设计资源： | NCP3127 Schematic NCP3127 BOM |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 最低可调至 0.8V |
| 电流 - 输出： | 2A |
| 输入电压： | 4.5 ~ 13.2 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 350kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | NCP3127 |
| 其它名称： | NCP3127CRAGEVBOS |
NCP3127
3.3 V
Output
Voltage
Output
Current
tss
Figure 28. Resistive Load Current
Layout Considerations
As in any high frequency switching regulator, layout is
very important. Switching current from one power device to
another can generate voltage transients across the
impedances of the interconnecting bond wires and circuit
traces. The interconnecting impedances should be
minimized by using wide short printed circuit traces. The
critical components should be located as close together as
possible using ground plane construction or single point
grounding. For optimal performance, the NCP3127 should
have a layout similar to the one shown in Figure 30. An
important note is that the input voltage to the NCP3127
should have local decoupling to PGND. The recommended
decoupling for input voltage is a 1 m F general purpose
ceramic capacitor and a 0.01 m F COG ceramic capacitor
placed in parallel.
Alternatively, if the output has an under voltage lockout,
turns on at a defined voltage level, and draws a consistent
current, then the RMS connected load current is:
PGND
Top
I CLI +
V OUT * V OUT_TO
V OUT
I OUT
(eq. 51)
BST
AGND
CP
CC
RC
492 mA +
3.3 V * 2.5 V
3.3 V
1A
VIN
ISET
VSW
COMP
FB
PGND
RF
R1
CF
I OUT
V OUT
V OUT_TO
= Output current
= Output voltage
= Output voltage load turn on
3.3 V
1.0 V
COG
0.01 uF
1 .0 uF
R2
AGND
PGND
Output
Voltage
CC
RC
CF
CP
RF
R2
R1
AGND
COMP
FB
PGND
COG
0.01 uF
BST
VIN
ISET
VSW
Output
Current
tss
t
AGND
Single Point
1 .0 uF
Bottom
Figure 29. Voltage Enable Load Current
If the inrush current is higher than the steady state input
current during max load, then an input fuse should be rated
accordingly using I 2 t methodology.
Grounding
Figure 30. Recommended Layout
The typical applications are shown in Figures 31
and NO TAG for output electrolytic and ceramic bulk
capacitors, respectively.
http://onsemi.com
20
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