参数资料
型号: NCP3163BSTEVB
厂商: ON Semiconductor
文件页数: 2/20页
文件大小: 0K
描述: EVAL BOARD FOR NCP3163BST
设计资源: NCP3163 Boost Eval Board BOM
NCP3163BSTEVB Gerber Files
NCP3163 Boost Eval Board Schematic
标准包装: 1
主要目的: DC/DC,步升
输出及类型: 1,非隔离
输出电压: 24V
电流 - 输出: 700mA
输入电压: 12V
稳压器拓扑结构: 升压
频率 - 开关: 300kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: NCP3163
其它名称: NCP3163BSTEVBOS
NCP3163, NCV3163
I PKsense
8
0.25 V
-
Current
Limit
9
Driver Collector
R SC
+
V CC
7
10
Timing Capacitor
6
V CC
Oscillator
Q1
11
Switch Collector
Shutdown
C T
R DT
5
R
Q
Q2
60
12
Gnd
Voltage Feedback 1
4
3
Thermal
45 k
S
Latch
V CC
2.0 mA
13
14
Switch Emitter
Feedback
Comparator
Voltage Feedback 2
LVI Output
2
1
LVI
+
+
-
+
+
-
1.25 V 15 k
1.125 V
(Bottom View)
V CC
7.0 V
15
16
Bootstrap Input
+
-
= Sink Only
Positive True Logic
Figure 2. Representative Block Diagram
PIN FUNCTION DESCRIPTION
SOIC16
1
2
3
4
6
7
8
9
10,11
14,15
16
5,12,13
Exposed
Pad
DFN18
15
16
17
18
1
3
4
5
6,7,8,9
10,11,12,13
14
2
Exposed
Pad
PIN NAME
LVI Output
Voltage Feedback 2
Voltage Feedback 1
GND
Timing Capacitor
V CC
I pk Sense
Drive Collector
Switch Collector
Switch Emitter
Bootstrap Input
No Connect
Exposed Pad
DESCRIPTION
This pin will sink current when FB1 and FB2 are less than the LVI threshold (V th ).
Connecting this pin to a resistor divider off of the output will regulate the application
according to the V out design equation in Figure 22.
Connecting this pin directly to the output will regulate the device to 5.05 V.
Ground pin for all internal circuits and power switch.
Connect a capacitor to this pin to set the frequency. The addition of a parallel resist-
or will decrease the maximum duty cycle and increase the frequency.
Power pin for the IC.
When (V CC ? V IPKsense ) > 250 mV the circuit resets the output driver on a pulse by
pulse basis.
Voltage driver collector
Internal switch transistor collector
Internal switch transistor emitter
Connect this pin to V CC for operation at low V CC levels. For some topologies, a
series resistor and capacitor can be utilized to improve the converter efficiency.
These pins have no connection.
The exposed pad beneath the package must be connected to GND (pin 4). Addi-
tionally, using proper layout techniques, the exposed pad can greatly enhance the
power dissipation capabilities of the NCP3163.
http://onsemi.com
2
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