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| 型号： | NCP3163PWR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 10/20页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK BOOST INV ADJ 16SOIC |
| 标准包装： | 1 |
| 类型： | 降压（降压），升压（升压），反相 |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 可调至 40V |
| 输入电压： | 2.5 V ~ 40 V |
| PWM 型： | 混合物 |
| 频率 - 开关： | 50kHz ~ 300kHz |
| 电流 - 输出： | 3.4A |
| 同步整流器： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽）裸露焊盘 |
| 包装： | 剪切带 (CT) |
| 供应商设备封装： | 16-SOIC W |
| 其它名称： | NCP3163PWR2GOSCT |
NCP3163, NCV3163
CB(min) + I D t + 4.0 mA on + 0.001 ton
When configured for step ? down or voltage ? inverting
applications (see application notes at the end of this
document) the inductor will forward bias the output rectifier
when the switch turns off. Rectifiers with a high forward
voltage drop or long turn ? on delay time should not be used.
If the emitter is allowed to go sufficiently negative, collector
current will flow, causing additional device heating and
reduced conversion efficiency.
Figure 12 shows that by clamping the emitter to 0.5 V, the
collector current will be in the range 10 m A over
temperature. A 1N5822 or equivalent Schottky barrier
rectifier is recommended to fulfill these requirements.
A bootstrap input is provided to reduce the output switch
saturation voltage in step ? down and voltage ? inverting
converter applications. This input is connected through a
series resistor and capacitor to the switch emitter and is used
to raise the internal 2.0 mA bias current source above V CC .
An internal zener limits the bootstrap input voltage to V CC
+7.0 V. The capacitor ’s equivalent series resistance must
limit the zener current to less than 100 mA. An additional
series resistor may be required when using tantalum or other
low ESR capacitors. The equation below is used to calculate
a minimum value bootstrap capacitor based on a minimum
zener voltage and an upper limit current source.
t
D V 4.0 V
Parametric operation of the NCP3163 is guaranteed over
a supply voltage range of 2.5 V to 40 V. When operating
below 3.0 V, the Bootstrap Input should be connected to
V CC . Figure 18 shows that functional operation down to
1.7 V at room temperature is possible.
Package
The NCP3163 is contained in a heatsinkable 16 ? lead
plastic package in which the die is mounted on a special heat
tab copper alloy pad. This pad is designed to be soldered
directly to a GND connection on the printed circuit board to
improve thermal conduction. Since this pad directly
contacts the substrate of the die, it is important that this pad
be always soldered to GND, even if surface mount heat
sinking is not being used. Figure 21 shows recommended
layout techniques for this package.
Vias to 2nd Layer Metal
for Maximum Heat Sinking
Exposed Pad
0.175
0.188
Minimum
Recommended
Exposed Copper
0.145
Flare Metal for Maximum Heat Sinking
Figure 21. Layout Guidelines to Obtain Maximum
Package Power Dissipation
APPLICATIONS
Figures 23 through 30 show the simplicity and flexibility
of the NCP3163. Three main converter topologies are
demonstrated with actual test data shown below each of the
equations for the key parameters. Additionally, a complete
application design aid for the NCP3163 can be found at
www.onsemi.com.
circuit diagrams. Figure 22 gives the relevant design
http://onsemi.com
10
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