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参数资料
| 型号： | NCP5181BAL36WEVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 4/12页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL NCP5181 36 W BALLAST |
| 设计资源： | NCP5181BAL36WEVB Schematic NCP5181BAL36WEVB Gerber Files NCP5181BAL36WEVB Bill of Materials |
| 标准包装： | 1 |
| 系列： | * |
NCP5181
ELECTRICAL CHARACTERISTICS (V CC = V boot = 15 V, V gnd = V bridge , ? 40 ° C < T A < 125 ° C, Outputs loaded with 1 nF)
Rating
Symbol
T A ? 40 ° C to 125 ° C
Units
OUTPUT SECTION
Min
Typ
Max
Output High Short Circuit pulsed Current
V DRV = 0 V, PW ≤ 10 m s, (Note 1)
Output Low Short Circuit Pulsed Current
V DRV = V CC , PW ≤ 10 m s, (Note 1)
Output Resistor (Typical Value @ 25 ° C Only)
Source
Output Resistor (Typical Value @ 25 ° C Only)
Sink
I DRVhigh
I DRVlow
R OH
R OL
?
?
?
?
1.4
2.2
5
2
?
?
12
8
A
A
W
W
DYNAMIC OUTPUT SECTION
Rating
Turn ? on Propagation Delay (V bridge = 0 V)
Turn ? off Propagation Delay (V bridge = 0 V or 50 V) (Note 2)
Output Voltage Risetime
(from 10% to 90% @ V CC = 15 V) with 1 nF Load
Output Voltage Falling Edge
(from 90% to 10% @ V CC = 15 V) with 1 nF Load
Propagation Delay Matching between the High Side and the Low Side
@ 25 ° C (Note 3)
Minimum Input Pulse Width that Changes the Output
Symbol
t ON
t OFF
t r
t f
D t
t PW
Min
?
?
?
?
?
?
Typ
100
100
40
20
20
?
Max
170
170
60
40
35
100
Units
ns
ns
ns
ns
ns
ns
INPUT SECTION
Low Level Input Voltage Threshold
Input Pulldown Resistor (V IN < 0.5 V)
High Level Input Voltage Threshold
V IN
R IN
V IN
?
?
2.3
?
200
?
0.8
?
?
V
k W
V
SUPPLY SECTION
V CC UV Startup Voltage Threshold
V CC UV Shutdown Voltage Threshold
Hysteresis on V CC
V boot Startup Voltage Threshold Reference to Bridge Pin
(V boot_stup = V boot ? V bridge )
V boot UV Shutdown Voltage Threshold
Hysteresis on V boot
Leakage Current on High Voltage Pins to GND
(V BOOT = V BRIDGE = DRV_HI = 600 V)
Consumption in Active Mode
(V CC = V boot , f sw = 100 kHz and 1 nF Load on Both Driver Outputs)
Consumption in Inhibition Mode (V CC = V boot )
V CC Current Consumption in Inhibition Mode
V boot Current Consumption in Inhibition Mode
V CC_stup
V CC_shtdwn
V CC_hyst
V boot_stup
V boot_shtdwn
V boot_shtdwn
I HV_LEAK
I CC1
I CC2
I CC3
I CC4
7.9
7.3
0.3
7.9
7.3
0.3
?
?
?
?
?
8.9
8.2
0.7
8.9
8.2
0.7
0.5
4.5
250
215
35
9.8
9.0
?
9.8
9.0
?
40
6.5
400
?
?
V
V
V
V
V
V
m A
mA
m A
m A
m A
*Note: see also characterization curves
1. Guaranteed by design.
2. Turn ? off propagation delay @ V bridge = 600 V is guaranteed by design
3. See characterization curve for D t parameters variation on the full range temperature.
4. Timing diagram definition see Figures 4, 5 and 6.
http://onsemi.com
4
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